Texas Instruments TMS320 DSP User Manual page 4

4 Algorithm Performance Characterization
4.1 Data Memory
4.1.1
4.1.2
4.1.3
4.2 Program Memory
4.3 Interrupt Latency
4.4 Execution Time
4.4.1
4.4.2
5 DSP-Specific Guidelines
5.1 CPU Register Types
5.2 Use of Floating Point
5.3 TMS320C6xxx Rules and Guidelines
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.4 TMS320C54xx Rules and Guidelines
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5 TMS320C55x Rules and Guidelines
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.6 TMS320C24xx Guidelines
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.7 TMS320C28x Rules and Guidelines
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
6 Use of the DMA Resource
6.1 Overview
4 Contents
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Heap Memory
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Stack Memory
Static Local and Global Data Memory
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MIPS Is Not Enough
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Execution Time Model
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Endian Byte Ordering
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Data Models
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Program Model
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Register Conventions
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Status Register
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Interrupt Latency
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Data Models
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Program Models
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Register Conventions
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Status Registers
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Interrupt Latency
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Stack Architecture
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Data Models
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Program Models
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Relocatability
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Register Conventions
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Status Bits
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General
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Data Models
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Program Models
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Register Conventions
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Status Registers
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Interrupt Latency
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Data Models
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Program Models
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Register Conventions
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Status Registers
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Interrupt Latency
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SPRU352G - June 2005 - Revised February 2007
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