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DDR SDRAM CAS Latency (2.5T)
These items set the timing and wait states for DDR SDRAM memory. We
recommend that you leave these items at the default value.
CPU/DRAM CLK Synch CTL (AUTO)
This option allows you set the CPU/DRAM synchronization. The valid options
are AUTO, Synchronous, and Asynchronous.
DRAM BackGround Cycles (Auto)
This option allows you to set the DRAM background cycles. The valid options
are AUTO, Delay 1T, and Normal.
LD-Off Dram RD/WR cycles (Auto)
This option allows you to set the LD-Off DRAM RD/WR cycles. Valid values
are AUTO, Delay 1T, and Normal.
Advanced DRAM control 2
Scroll to this item and press <Enter> to view the following screen:
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
CS[5:0]# Hold Time CTL
DQS/CSB Hold Time CTL
- ¯ ® ¬
: Move
Enter : Select
F5:Previous Values
CS[5:0]# Hold Time CTL (+0.5 ns)
This option allows you to set the CS Hold Time. Valid values are +.05 ns,
+.1.0 ns, +1.5 ns, and +2.0 ns.
DQS/CSB Hold Time CTL (+0.5 ns)
This option allows you to set the DQS/CSB Hold Time. Valid values are +.05
ns, +.1.0 ns, +1.5 ns, and +2.0 ns.
Press <Esc> to return to the Advanced Chipset Features screen.
Memory Hole at 15M-16M (Disabled)
This item is used to reserve memory space for ISA expansion cards that re-
quire it.
AGP Fast Write Control (Enabled)
This item allows you to enable or disable the caching of display data for the
video memory of the processor. Enabling can greatly i m prove the display
Advanced DRAM Control 2
[+0.5 ns]
[+0.5 ns]
Menu Level
+/-/PU/PD:Value:
F10: Save
ESC: Exit
F6:Fail-Safe Defaults
F7:Optimized Defaults
34
Item Help
F1:General Help
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