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Operation Complete (*OPC)
The IEEE 488.2 structure provides one technique which can be used to find
out if any operation is finished. The *OPC command, when sent to the
instrument after the operation of interest, sets the OPC bit in the Standard
Event Status Register when all pending device operations have finished. If
the OPC bit and the RQS bit have been enabled, a service request is
generated.
OUTPUT 707;"*SRE 32 ; *ESE 1"
OUTPUT 707;":DIG CHAN1 ; *OPC"
Trigger Bit (TER)
The Trigger (TER) bit indicates if the device has received a trigger. The TRG
event register will stay set after receiving a trigger until it is cleared by
reading it or using the *CLS command. If your application needs to detect
multiple triggers, the TER event register must be cleared after each one.
If you are using the Service Request to interrupt a program or controller
operation when the trigger bit is set, then you must clear the event register
after each time it has been set.
OUTPUT 707;"*SRE 32"
OUTPUT 707;"*ESE 2"
OUTPUT 707;":TER?"
ENTER 707;A$
Status Byte
If the device is requesting service (RQS set), and the controller serial polls
the device, the RQS bit is cleared. The MSS bit (read with *STB?) is not
cleared by reading it. The status byte is not cleared when read, except for the
RQS bit.
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!enables OPC service request
!initiates data acquisition,
!and
!generates a SRQ when the
!acquisition is complete
! enables event status register.
! the next trigger will generate an SRQ.
! enables event status register
! queries the TRG event register, thus
! clearing it.
! the next trigger can now generate an
! SRQ
Status Reporting
6–5
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