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Table 12. lists the corresponding PLB Master interface requests generated in response to processor re-
quests which target the PLB.
Processor to PLB Transfer
Read 1-4 Bytes
Word Address 0
CPU_A(29:31)=000
Read 1-4 Bytes
Word Address 1
CPU_A(29:31)=100
Read 2-8 Bytes
Crossing Word Boundary
Read 32 Bytes
(8 Word Line)
Write 1-4 Bytes
Word Address 0
Write 1-4 Bytes
Word Address 1
Write 2-8 Bytes
Crossing Word Boundary
Write 32 Bytes
(8 Word Line)
3.8 Processor - Address Only Cycles
The CPC700 supports all processor generated Address Only cycles. In response to a processor Address
Only cycle, CPC700 acknowledges the cycle and takes no other action. As a result, CPC700 does not prop-
agate any Address Only cycles beyond the processor bus interface.
3-10
Table 12. Processor to PLB Cycle Translation
PLB Transfer
32-bit Slave Responds
1-4 byte read w/byte enables,
Read data transferred to CPU_DATA[0:31]
1-4 byte read w/byte enables,
Read data transferred to CPU_DATA[32:63]
2-8 byte read w/byte enables,
Request W0 Read data, transfer to CPU_DATA[0:31]
Request W1 Read data, transfer to CPU_DATA[32:63]
8 word line read consisting of 8 PLB data phases,
Read data transferred to CPU_DATA[0:63]; indicate word being trans-
ferred. Only 1 word transferred per PLB data phase
Not applicable to PCI
1-4 byte write w/byte enables,
Write data transferred from CPU_DATA[0:31]
1-4 byte write w/byte enables and data replicated on Word Lane 0,
Write data transferred from CPU_DATA[32:63]
2-8 byte write w/byte enables,
Request W0 Write, transfer data from CPU_DATA[0:31]; queue PLB
write for W1; request PLB; request W1 Write, transfer data from
CPU_DATA[32:63]
8 word line write consisting of 8 PLB data phases,
Write data transferred from CPU_DATA[0:31] for Word 0 and from
CPU_DATA[32:63] for Word 1.Only 1 word transferred per PLB data
phase
Not applicable to PCI
Processor Interface
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