Table of Contents
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Index
BRDH 9-6
BRDL 9-6
Bridge Configuration 5-19
character mode
NS16450 1-9, 7-1
Clocking 6-1
Completion Ordering 5-17
Errors 5-44
Features 1-1
FIFO 7-11
FIFO control register 7-7
description 7-7
FIFO operation
interrupt mode 7-11
polled mode 7-12
GEAR 13-1
General Purpose Timers 9-1
I/O Drivers 11
IIC 8-1
Initialization Sequence 4-5
Internal Peripherals Interface Signals 2-6
Interrupt Controller 10-1
interrupt enable register
description 7-9
interrupt identification register
description 7-8
Interrupts 8-15
JTAG 11-1
line control register
description 7-5
line status register 7-6
Memory Access Arbiter 4-4
Memory Controller 4-1
Memory Interface Singals 2-5
CPC700 User's Manual—Preliminary
B
C
E
F
G
I
J
L
M
Overview 1-1
PACR 12-2
Page Mode Access 4-5
parallel-to-serial conversion 1-8, 7-1
PCI Bus Interface Signals 2-3
PCI Interface 5-1
PCI Interface Address Maps 5-4
PCI Master 5-13
PCI Target Interface 5-8
PEAR 12-2
PESR 12-3
PLB 12-1
PLB Address Map 5-4
PLB arbiter
registers 12-2
PLB to OPB bridge
registers 13-1
Pll Tuning 6-1
Power Management 6-1
Processor Bus Arbiter 3-11
Processor Interface 3-3
Processor Interface registers 3-2
Processor Interface Signals 2-1
processor local bus 12-1
register description 7-3
summary 7-4
Registers 14-1
registers
BRDH 9-6
BRDL 9-6
GEAR 13-1
PACR 12-2
PEAR 12-2
PESR 12-3
PLB arbiter 12-2
PLB to OPB bridge 13-1
SPCTL 9-6
SPHS 9-6
SPLS 9-9
SPRB 9-9
SPRC 9-7, 10-5, 10-6, 10-7, 10-8, 10-9
O
P
R
Index-1
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