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5.9.2.2 PCI Configuration Address Register (PCICFGADR)
Address Offset: FEC0_0000h
Width:
32
Reset Value:
00000000h
Access:
Read/Write
This register controls what type of cycle is generated when PCICFGDATA is accessed. Its fields are shown
in Figure 41..
31 30
Reserved
Enable bit ('1' = enabled)
See the PCI 2.1 Spec for details about how the fields are used.
5.9.2.3 PCI Configuration Data Register (PCICFGDATA)
Address Offset: FEC0_0004h
Width:
32
Reset Value:
00000000h
Access:
Read/Write
Accesses to PCICFGDATA cause one of three things to happen depending on the value of PCICFGADR:
1.
Generate a Type 0 Configuration Cycle on the PCI bus. This happens when the Bus Number is
ZERO and the Device Number is greater than ZERO. During the address phase of the configuration
cycle, AD11 is asserted if the Device Number is 1, AD12 is asserted if the Device Number is 2, etc.
AD11 through AD31 are all low if the Device Number is 22 through 31.
2.
Generate a Type 1 Configuration Cycle on the PCI bus. This happens when the Bus Number is
greater than ZERO.
3.
Access a CPC700 PCI Configuration Register within the CPC700. This happens when the Bus
Number is ZERO and Device Number is ZERO.
5.9.3 PCI Interface Configuration Registers
These registers can be accessed by both the processor and the PCI (if enabled). They are accessed by the
PCI with Configuration Type 0 cycles when the IDSEL input of the CPC700 is active.
5-26
24 23
16 15
Bus Number
Figure 41.Format of PCICFGADR Register
11 10
8
Device
Function
Number
Number
7
2
1
0
Register
0
0
Number
PCI Interface
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