Chapter 12. Processor Local Bus (Plb); Plb Master Priority Assignment; Table 100. Cpc700 Plb Master Assignments; Table 101. Registers Controlling Plb Master Priority Assignments - IBM CPC700 User Manual

Chapter 12. Processor Local Bus (PLB)

The PLB is a high-performance on-chip bus. The PLB supports read and write data transfers between
master and slave devices equipped with a PLB interface and connected through PLB signals.
Access to the PLB is granted through a central arbitration mechanism that enables masters to
compete for bus ownership. This arbitration mechanism provides for the implementation of several
priority schemes.
Table 100 lists the PLB masters provided in the CPC700.
The CPC700 has the following PLB slaves:
• 60x-PLB Processor Interface
• PCI
• OPB Bridge

12.1 PLB Master Priority Assignment

Each PLB master can be assigned one of four priority levels to be used during PLB transfers. The
60x-PLB Processor Interface is hardwired to the highest PLB priority level and thus its priority level
cannot be changed. The default PLB priority level of the PCI PLB Master is also the highest, but it can
be changed by software.
A register associated with each master controls the priority of that master. Table 101 lists the PLB
masters and the register fields controlling the priority of the masters. Priorities range from 0b00
(lowest) to 0b11 (highest).

Table 101. Registers Controlling PLB Master Priority Assignments

Master ID
60x-PLB Processor Interface
0
PCI
1
See Figure 65, "PLB Arbiter Control Register (PACR)" on page 12-2 for information about
programming the PACR to control PLB priority mode and priority order, which determine how the PLB
arbitrates simultaneous PLB bus access requests having equal priorities.
CPC700 User's Manual—Preliminary

Table 100. CPC700 PLB Master Assignments

Master ID
60x-PLB Processor Interface
0
PCI
1
Description
Description
Register Field
PRIFOPT1[4:5]
PCI BRDGOPT1[6:5]
Comments
Hardwired. Not
programmable.
Software programmable.
Reset value is 0b11.
12-1