National Instruments DAQPad-6508 User Manual page 72

DPA
DPB
DPC
DRAM
drivers
DSP
dual-access memory
dual-ported memory
dynamic range
E
ECL
EEPROM
EGA
EISA
EMC
EPROM
event
expansion ROM
external trigger
© National Instruments Corporation
bidirectional data lines for Port A of PPI D
bidirectional data lines for Port B of PPI D
bidirectional data lines for Port C of PPI D
dynamic RAM
software that controls a specific hardware device such as a DAQ board or a
GPIB interface board
digital signal processing
memory that can be sequentially accessed by more than one controller or
processor but not simultaneously accessed. Also known as shared memory.
memory that can be simultaneously accessed by more than one controller
or processor
the ratio of the largest signal level a circuit can handle to the smallest signal
level it can handle (usually taken to be the noise level), normally expressed
in decibels
emitter-coupled logic
electrically erasable programmable read-only memory
enhanced graphics adapter
Extended Industry Standard Architecture
electromechanical compliance
erasable programmable read-only memory—ROM that can be erased
(usually by ultraviolet light exposure) and reprogrammed
the condition or state of an analog or digital signal
an onboard EEPROM that may contain device-specific initialization and
system boot functionality
a voltage pulse from an external source that triggers an event such as A/D
conversion
G-7
Glossary
DAQPad-6507/6508 User Manual