Npd Electronics Circuit Description - Scion Instruments 436-GC Service Manual

436-GC/456-GC

NPD Electronics Circuit Description

Power supplies and grounds.
There are four grounds serving the NPD electronics circuitry. Ground 1 is the return for the +5V digital
supply. It is connected directly to Ground 4, the unregulated +24V return, at the card edge connector on
the Mother board. The analog return is Ground 2, which provides a low-noise return for the ±15V, -5V, and
+5.25V supplies. Ground 3 is the reference for analog signal distribution, which carries almost no DC
current. All of the grounds must be tied together externally for the board to function properly.
Four RC filters remove noise from the analog power supplies. These consist of R13 with C16, R12 with
C15, R10 with C13, and R11 with C14.
Digital circuits.
U4 decodes bus address information to access latch U3, DAC U6, and buffer U2. The latch holds all of the
digital control signals for the board, while the buffer transmits the board identification number and serial
data from EEPROM U5 to the bus. R18 and R20 set the desired operating logic levels, while allowing the
inputs to be pulled high or low for test purposes.
The EEPROM is a 1024-bit device which is used to store calibration data. Software has full control over the
serial interface, consisting of the chip select, shift clock, and data inputs (pins 1 - 3, respectively), and must
reassemble the stored data from the serial output stream coming from pin 4. When the EEPROM is not
selected, its output is high impedance. R19 provides a positive level to CMOS buffer U2 in this case.
Input log amplifier of square-root electrometer.
The electrometer is a multi-stage circuit which produces an output voltage that is proportional to the
square-root of the input current. This is accomplished by three amplifier stages, AR1 (dual) and AR2,
having logarithmic and exponential responses. The nonlinear responses are generated by the fundamental
characteristic of bipolar transistors, which is represented in the following equations:
v = (nkT/q) log(I
be
where v = base-emitter voltage (volts)
be
n = emission coefficient (near 1.00)
k = Boltzmann's constant (1.38E-23 Joule/K)
T = Temperature (Kelvins)
q = electron charge (1.6E-19 coulomb)
le = collector current
I saturation current
sat
e = base of natural logarithms
Input amplifier AR2 has an extremely high input impedance, with a bias current of only about 40fA (40 x 10-
15A). All of the input current from J1 must therefore be supplied from the collector of Q1 (pin 8).
Negative feedback from the output of AR2 adjusts the base-emitter voltage of Q1 until precisely this
current flows into the collector. The output voltage from this stage, which is taken from the emitter of Q1
(pin 6), is therefore v
(1µA), where the impedance looking into the emitter of Q1 has dropped to 26k.
Since the non-inverting input of AR2 is grounded, the inverting input remains at ground also, keeping the
collector of Q1 at ground. This holds the collector-base voltage at zero, which is a necessary condition for
the equations above to apply. The input connection at J1 also remains near ground at low input currents,
minimizing noise due to variations in input capacitance. R1 limits input current if an excessive voltage is
applied to the input, but it also allows the input voltage to rise slightly at the higher input currents.
R2, which isolates the amplifier input from the input cable capacitance for loop stability, has almost no DC
voltage drop across it, since only the bias current of AR2 flows through it. C3 also enhances loop stability,
and reduces high-frequency noise.
SCION Instruments
qv
/I + 1) or l = I (e( be
c sat c sat
l=(nkT/q) log(I /I + 1). R4 stabilizes the loop gain at input currents near full scale
eb in sat
436-GC/456-GC Service Manual Revision B February 2019
/nkT
) _ 1),
610 Hardware description
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