IMS 740 Manual

IMS INTERNATIONAL
MODEL 740
I/O PROCESSOR BOARD
* A
GENERAL DESCRIPTION
The Model 740 I/O PROCESSOR is a single board computer with a Z-80A processor,
64K bytes of Dynamic RAM with Parity, 2K bytes of IPL PROM, Two programmable
Synchronous/Asynchronous communication channels with MODEM control, Ten
programmable parallel I/O lines compatible with Bell 801 Automatic Calling Unit, Four
interval timers ( two used for baud rates), Z-80 internally-prioritized vectored
interrupt structure, and Parallel interface to the S-100 BUS Host processor.
The Z-80A SIO interfaces the Z-80A CPU to Two asynchronous or synchronous Serial
Data Channels. The SIO converts input serial data from the RS-232C port to parallel
data to be acted upon by the system. Output data is converted from parallel to
serial data to be placed on the RS-232C port.
The 8255A Programmable Peripheral Interface circuit interfaces the S-100 BUS to the
slave Z-80 A CPU bus.
The MODEL 740 I/O Processor consists of a single printed circuit board that occupies
one slot in the Series 5000 or 8000 Computer Systems. Each serial RS-232C port is
brought out to a 3M 26-pin header. The RS-232C ports are designed as Data Terminal
Equipment (DTE) to connect directly to a MODEM. To connect a terminal directly to
the RS-232C port (DTE to DTE) the RS-232C cable wires must be interchanged for
proper operation of terminal.
S-100 BUS TO I/O PROCESSOR INTERFACE
8255A Mode 2 S-100 BUS to Slave Z-80A CPU Interface
Due to the drastic reduction of hardware costs, system designs which utilize multiple
CPU modules are becoming more common. A Model 451 Z-80A CPU is configured as
the master S-100 CPU and used to control multiple Z-80A slave modules which act as
intelligent I/O controllers. When multiple CPUs are utilized, a method of processor
intercommunication must be supported. The IMS 740 Z-80A module is implemented as a
master/slave interface through the use of the 8255A Mode 2 bidirectional bus.
The S-100 BUS interface is supported by an 8255A which is configued in Mode 2. The
8255A is selected through the use of a standard S-100 I/O Address decode select
s c h e m e and the S-100 vector interrupt structure. The Z-80A slave logic is
implemented to allow the slave Z-80A CPU to generate the ACK- and STB- signals
required to READ from and WRITE to the 8255A bidirectional bus.
IMS INTERNATIONAL
D00740 REV 1.0 October 20, 1981 Page 1