IMS IMSAI 8080 User Manual

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IMS ASSOCIATES, INC.

USER MA

IMSAI8080

IMSAI

Summary of Contents for IMS IMSAI 8080

Page 1 IMS ASSOCIATES, INC. USER MA IMSAI8080 IMSAI...
Page 2 IMSAI 8080 System General Assembly and Test Instructions INTRODUCTION This chapter contains the following sections: Kit Unpacking Instructions Construction Hints - general notes on how to build your kit. Recommended Overall Order of Assembly (includes cross-reference to chapters where specific assembly instructions for the various submodules will be found).
Page 3 Test Instructions KIT UNPACKING INSTRUCTIONS Remove all packages from the outer box. For a standard IMSAI 8080 kit, these will consist of: Documentation Set (Manual plus two books) Cabinet Base Plate Table Top Cover (or Rackmount cover and Rackmount painted pieces) Two large inner boxes Two small inner boxes.
Page 4 IMSAI 8080 System General Assembly Notes CONSTRUCTION HINTS GENERAL The IMSAI 8080 microcomputer is a complex piece of electronic equipment. This section covers a number of items, each of which must be followed to insure a working system at the completion of assembly.
Page 5 IMSAI 8080 boards. Obtain some extra #20 hook-up wire and solder locally and solder pieces together until you feel comfortably able to quickly make a good joint.
Page 6 IMSAI 8080 System General Assembly Notes Solder Using the proper solder is as important as using the proper iron, and there are many solders to choose among. In normal electronics assembly, separate paste or liquid flux is not used. Rather, . a solder with a "core” of rosin (or resin) base flux is Used.
Page 7 IMSAI 8080 System General Assembly Notes see the solder flow onto the two surfaces. It should flow around the lead, and if you see that the solder has flowed only on one side of the lead, the iron should be re-applied (while watching the joint) to heat the joint enough for the solder to flow.
Page 8 IMSAI 8080 System General Assembly Notes a joint is to be made immediately. If a tip becomes oxidized, dipping it in a can of rosin flux is usually sufficient to enable solder to flow on it again. They may be cleaned of oxide by fine steel wool or other abrasive, but a plated tip should never be filed.
Page 9 IMSAI 8080 System General assembly Notes much as possible, and always touch the chip's container or surface which it is touching before picking up the chip. Also touch a surface or container before placing the chip back in it. Touch a PC board before inserting the chip.
Page 10 IMSAI 8080 System General Assembly Notes The board or the chip is v^ry likely to be damaged if there is a need to unsolder a chip that was soldered in with Pin 1 in the wrong direction. Unless you are completely sure...
Page 11 IMSAI 8080 System General Assembly Notes MOUNTING COMPONENTS Integrated Circuit Chips. (IC's) Some of the chips come in a little plastic rectangle with an open bottom and top. These can be used as inserters by setting the carrier with the chips on a piece of felt or...
Page 12 IMSAI 8080 System General Assembly Notes bent slightly to hold the I.C. in the board while soldering. Take special care on each and every chip to observe the following points: That Pin one is in the correct direction. Refer to marking on the board or assembly instructions to de...
Page 13 IMSAI 8080 System General Assembly Notes Discrete Components Resistors and diodes can be installed most neatly using a lead bender to bend the leads consistently. Most pads for this sort of component are .5" apart. Disc ceramic capacitors often have the dipped insulation extending down the leads a short distance, preventing these from being pulled down all the way to the board.
Page 14 IMSAI 8080 System General Assembly and Test Instructions RECOMMENDED ORDER OF ASSEMBLY Described In Step Description MPU Chapter Assemble MPU and RAM boards. Check care fully. RAM Chapter Assemble CP-A including switches and CP-A Chapter flat cable. Check carefully. PS-C Chapter Assemble electronic components on Power Supply.
Page 15 IMSAI 8080 System General Assemoiy and Test Instructions MAINFRAME ASSEMBLY Assembly of the mainframe consists of the following steps: •Power supply installation •Mother board installation •Connection between power supply and mother board •Installation of CP-A panel. •Connection of power supply and front panel POWER SUPPLY INSTALLATION Remove #8 hardware from transformer on Power Supply p.c.
Page 16 r - V," - 20 x 1! V." - 20 x 114" BOLT 8 - 32 x IX" MACHINE SCREW TRANSFORMER r K" -: 20 NUT FOOT 8 - 32 NUT 14" SPLIT LOCK WASHER x 1/16 FLAT WASHER No. 8 STAR LOCKWASHER ID X 1/16"...
Page 17 I MSA I 8080 SYSTEM GENERAL ASSEMBLY AND TEST INSTRUCTIONS MOTHERBOARD MOUNTING SYSTEM 6— 3 2 x * " NYLON SCREW 4 PER E X P -4 8 PER E X P -6 24 PER E X P -2 2 MAINFRAME ASSEMBLY FIGURE 2...
Page 18 IMSAI 8080 System General Assembly and Test Instructions 2 or 3 #14 or #12 gauge w i r ® from ground plane to ground bus on Mother board. 2 #18 gauge wires from External Switch pads to power switch on CP-A or on back panel.
Page 19 IMSAI 8080 System General Assembly and Test Instructions With the Power Supply checked out and operating properly, the rest of the system is ready to be tested. The MPU board should be inserted in the slot behind the front panel with the flat cable...
Page 20 IMSAI 8080 General Assembly and Test Instructions should be raised momentarily to the EXAMINE position and released. Check that the lights after this operation are exactly the same as described for after the RESET switch was operated. The machine is now ready to enter a small test program.
Page 21 IMSÄI 8080 General Assembly and Test Instructions The address is now at 0 as indicated by the lights labelled ADDRESS BUS. Into position 0 we wish to put an input instruction. The bit pattern for the input instruction must be set in the center group of switches labelled ADDRESS-DATA.
Page 22 IMSAI 8080 General Assembly and Test Instructions The EXAMINE switch, can again be raised momentarily with the address switches all down, to return the machine to position 0, once it has been determined that all lines listed in Test Program One are stored correctly in the memory.
Page 23 IMSAI 8080 General Assembly and Test Instructions The Status Byte will again have MEMR,M1, and WO lights lit and the others of i f . When the single step switch is operated once again, the processor is permitted to complete the cycle during which it reads in the output instruction and begin the next cycle during which it will read the address of the output device.
Page 24 IMSAI 8080 General Assembly and Test Instructions which should now appear on the lights on the data bus indicators. As the SINGLE STEP switch is operated again, permitting the processor to complete the fetch of the jump instruction, and start the next cycle of executing...
Page 25 IMSAI 8080 General Assembly and Test Instructions and easy to provide a circuit modification such that when the data was put out as a 1 the light -would be lit rather that turned off, such as addition to the circuit would have cost you more that the cost for byte of memory.
Page 26 It is a game program using the INPUT switches and the PROGRAMMED OUTPUT lights on the IMSAI 8080 front panel. A pattern of lights in the PROGRAMMED OUTPUT ports is moved to the left one bit at a time, and the left hand bit which is "pushed off"...
Page 27 IMSAI 8080 General Assembly and Test Instructions appropriate, no further switch movements will affect the condition of any of the lights until the next shift to the left has occurred. This was done to give the switches time to stop bouncing and stay closed as the...
Page 28 IMSAI 8080 General Assembly and Test Constructions Figure 1 shows the structural blocks in the processor which are important to the programmer. Central to the processor’s operation is the register named the ACCUMULATOR. This register and all the others is like one eight bit position in memory or a small "blackboard"...
Page 29 IMSAI 8080 General Assembly and Test Instructions Some of the STATUS BITS are affected by the operations in other registers than the ACCUMULATOR. For instance the carry bit is affected by additions made in the H and L registers by using the double add instructions.
Page 30 8080 PROCESSOR FIG. 1...
Page 31 IMSAI 8080 General Assembly and Test Instructions F I G . 2...
Page 32 START FIG. 3 GAME PROGRAM BASIC FLOWCHART 0 7 C H U C A —...
Page 33 General Assembly and Test Instructions GAME PROGRAM LISTING OCTAL DESCRIPTION MNEMONIC ADD. INST. ADD. INST. 000 000 0000 XRA, A .Exclusive OR A to itself (put zero in A) MOV H, A Move A to H (put zero in H) Input data from front panel switches Move A to L...
Page 34 Exclusive OR of two switch patterns results in I’s in positions which were changed, with ail 0’s elsewhere. B= DISPLAY BYTE STORAGE C=SWITCH DEBOUNCE INDICATOR l=DEBOUNCE 0=NORMAL OPERATION D=LAST SWITCH SETTINGS E=CURRENT SWITCH SETTINGS H,L=DELAY COUNTER SP=INCREMENT FOR DELAY COUNTER c) 3975 IMS Assoc Inc • A...
Page 36 IMSAI 8080 System Cabinet Assembly Instructions CABINET ASSEMBLY INSTRUCTIONS Begin by installing the correct number of plastic card guides on the chassis part C's. The card guides should be placed from the front backwards, an equal number on each piece C, taking care that the wedge - shaped opening of the slot is positioned upwards.
Page 37 IMSAI 8080 System Cabinet Assembly Instructions the two card frames between the front and back frames. Use two 6— 32x5/16” machine screws at each end of each card frame. The front and back frames have slotted holes allowing the card frames to be adjusted slightly when the Mother board is installed on the base plate and boards are inserted in the card frames.
Page 38 IMSAI 8080 System Cabinet Assembly Instructions RACK MOUNT SYSTEM ASSEMBLY INSTRUCTIONS For the rack mount system, begin by installing the rack mount cover on the chassis. Use five 6-32x5/16" Phillips pan head machine screws. Next install the left and right side plates to the chassis with the front flanges pointing outwards.
Page 40 8080 Hack Mount Parts List IMS AI ITEM PART # QUANTITY DESCRIPTION Rack Mount Front Panel Rev. C 93-3010008 Rack Mount Left Slide Rev. C 93-3070001 93-3070002 Rack Mount Right Slide Rev. 0 93-3010012 Rack Mount Cover Rev. B Screw 20-3302001 6-32x5/16"...
Page 41 8080 Chassis Parts List IMS AX ITEM PART # QUANTITY DESCRIPTION/IDENTIFYING MARKS Back Frame 93-3010003 Back Frame "Al" Front Piece Painted Front Piece ”A2B" 93-3010010 Cabinet Base 93-4010004 Cabinet Base "A3" Front Frame 93-3010001 Front Frame "B" Card Frame 93-3010002 Card Frames "C"...
Page 44 Mother Board Functional Description MOTHER BOARD FUNCTIONAL DESCRIPTION The IMSAI 8080 system Mother boards are available in three different length sections varying from a minimum of 4 printed circuit card connector positions. The basic system includes a Mother board with six connector positions on it.
Page 46 T O P G N D...
Page 48 T O P G N D nat'l • volts EXP 6...
Page 50 EXP-?° Rev. 1...
Page 52 EXT ( E X t E ^ E R BOARD)
Page 54 Mother Board Parts List EXP-4 IMSAI ITEM QUANTITY DESCRIPTION/IDENTIFYING MARKS PART # PC Board 92-0000004 4-Slot Printed Circuit Board #6 Sholder Fiber Washer Washer 21-3330001 6 - 3 2 x V Threaded Spacer Spacer 21-4600001 21-3120001 6-32 Nut 6-32x3/4” Nylon Screw Screw 20-3701002 EXP-6...
Page 55 Mother Board Assembly Instructions MOTHER BOARD ASSEMBLY INSTRUCTIONS The Mother board appears to be the simplest of all the boards to assemble. The solder mask minimizes the chances of shorting ad jacent traces. However, it is imperative that extra care be taken during assembly to avoid excess solder shorting adjacent pins.
Page 56 Mother Board Assembly Instructions SOCKET INSERTION The 100 pin edge connectors are symmetrical so that they may be inserted either way. The connector stands off the board slightly supported by raised feed at each end. Each connector should be checked during assembly to make sure that it is seated properly and that the Mother board near the center of the connector is neither pushed further toward the connector nor lifted away before the connector is soldered in place to prevent the Mother board from...
Page 57 Mother Board User Guide Mother Board USER GUIDE With the proper care taken during assembly, the Mother board should be the most reliable board in the system. The only attention the user will typically put on the Mother board, is when he desires to add more card slot positions.
Page 58 IM5AI 8080 BUS SIGNAL LIST +16v -16v SSW DSU XRDY V I 0 EX T CLR V I I V I 2 V I 3 V I 4 5« V I 5 V I 6 V I 7 M A I Ub UMSL MW RITE il'tÖ...
Page 60 Mother Board User Guide BUS DEFINITION Front Side SYMBOL NAME F U N C T I O N Interrupt Vectored Line # 1 Vectored Interrupt Line #2 Vectored Interrupt Line #3 Vectored Interrupt Line #4 Vectored Interrupt Line #5 Vectored Interrupt Line #6 Vectored...
Page 61 Mother Board User Guide BUS DEFINITION Front Side N o . SYMBOL NAME FUNCTION ADDR DSBL ADDRESS DISABLE Allows the buffers for the 16 address lines to be tri- stated DO DSBL DATA OUT DISABLE Allows the bidirec tional data bus drivers for the 8 data lines to be tri- stated for both in...
Page 62 Mother Board User Guide BUS DEFINITION Front Side SYMBOL NAME FUNCTION Address Line #5 Address Line #4 Address Line #3 Address Line #15 Address Line #12 Address Line #9 Data Out Line #1 Data Out Line #0 Address Line #10 Data Out Line #4 Data Out Line #5 Data Out Line #6...
Page 63 Mother Board User Guide BUS DEFINITION Front Side SYMBOL NAME FUNCTION SNIP Status output signal which indicates that that the address bus contains the address of an input device and the input data should be placed on the data bus when PDBIN is active SMEMR MEMR...
Page 64 Mother Board User Guide BUS DEFINITION Back Side SYMBOL NAME F U N C T I O N CGND CHASSIS GROUND UNUSED MWRT MEMORY WRITE From the Front Panel indicates that the current data on the Data Out Bus is to be written into the memory location cur...
Page 65 Mother Board User Guide BUS DEFINITION Back Side SYMBOL NAME FUNCTION PINT INTERRUPT The processor recog REQUEST nizes an interrupt request on this line at the end of the current instruction or while halted. If the processor is in the HOLD state or the Ihterrupt Enable flip-flop is reset, it will not honor...
Page 66 Mother Board User Guide BUS DEFINITION Back Side SYMBOL NAME FUNCTION WRITE C o n 't .: data on the data bus is stable while the PWR is active PDBIN DATA BUS IN Processor control output signal indi cates to external circuits that the data bus is in the input mode...
Page 67 Mother Board User Guide BUS DEFINITION Back Side SYMBOL NAME FUNCTION SINTA INTA Status output signal to acknowledge sig nal for INTERRUPT request Status output signal indicates that the operation in the current machine cy cle will be a WRITE memory or output function SSTACK...
Page 70 POWER SUPPLY PS-28U FUNCTIONAL DESCRIPTION------------------------------ The IMSAI PS-28U is a modular, unregulated power supply for the IMSAI 8080 System. It provides the basic unregulated +8, +16, and -16 system supply voltages and can be configured for the following AC input voltages at either 50 or 60 Hz: 92, 103.5, 115, 126.5, 184, 207, 23Ö, and 253 VAC...
Page 71 POWER SUPPLY PS-28U Theory of Operation Revision 1 At 100 VAC, 50 Hz, resistive load: 25.0 amperes at +7.0 volts ripple valley 4.0 amperes at +13.5 volts ripple valley 4.0 amperes at -13.5 volts ripple valley THEORY OF OPERATION- The PS-28U is an unregulated power supply that provides the basic +8, +16, and -16 voltages for the 8080 system.
Page 72 PS-28U Parts List BOAST): PS-C IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM PART # 15-0000001 Rosin Core Solder 5 ’ Wakefield 690—220-P, Modified 16-0100006 Heat Sink 6-32x3/8" Phillips Pan Head Machine Screw 20-3402001 6-32x3/4" Phillips Pan Head Machine Screw 20-3702001 Screw 8-32x3/8" Binding Head Machine 20-4401001 Screw 8-32xlV Binding Head Machine...
Page 73 PS-280 Parts List IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM PART # 18 AWG, Orange, Gavitt 8522 60” Wire 22-1018001 18 AWG, Yellow, Gavitt 8522 Wire 60" 22-1018002 Twisted Pair, 18 AWG, Yellow/orange, Wire 22-5018001 12” Stranded and Insulated Line Cord 22-6000001 Beiden 17239 Strain Relief Bushing Grommet Grommet...
Page 74 POWER SUPPLY PS-28U Assembly Instructions ASSEMBLY INSTRUCTIONS— ------------------------------ 1. Unpack your board and check all parts against the parts lists enclosed in the package. COMPONENT INSTALLATION 2. Insert and solder each of the two IK Ohm, % watt resistors (brown, black, red) at locations R1 and R2 as shown on the Assembly Diagram.
Page 75 POWER SUPPLY PS-28U Assembly Instructions Primary B Primary A Pin 6 Common Pin 1 Common Pin 7 20% Lo Line Pin 2 20% Lo Line Pin 8 10% Lo Line Pin 3 10% Lo Line Pin 9 Nominal Pin 4 Nominal (115/230 VAC) (115/230 VAC) Pin 10 10% Hi Line...
Page 76 POWER SUPPLY PS-28U Assembly Instructions ( ) 12. Attach a crimp terminal to a 3 inch piece of #14 black wire. Solder one end to the ground trace below lug #14 and then attach the crimp terminal to lug #14. { ) 13.
Page 77 POWER SUPPLY PS-28U Assembly Instructions ( ) 17. Attach a crimp terminal to the wire from CRO and CRl. Connect it to terminal #15 of the transformer. ( ) 18. Repeat above (#17) procedure for black wire from CR2 and CR3 and connect it to terminal #13 of the transformer.
Page 78 YELLOW TWIST YELLOW TWIST 'P,"N3 © © ACIN ACIN 103 VAC 92 VAC ±594 - * i u 3 I 5 > < § > □ < < f t * fwwijr W W l s J F < S > .10% I.Q-LINE___ 20% LO LINE FRONT VIEW...
Page 80 WIRING CHART: 115 - 126 VAC 60 Hz IN Use next lowest line input taps when operating full chassis or on 50 Hz. See User Guide for more information. Use 5A fuse. © 1977 IMSAl MFG. CORP. SAN LEANORO, CA. ALL RIGHTS HESERVED WORLDWIDE MADE IN U.S.A.
Page 82 - ' s YELLOW TWIST YELLOW TWIST — S AC IN A C IN © 207 VAC 164 V A C f t n ( “l ±5% M S J ^ S J iy 12J I2f 20% 1,0 L IN E t £...
Page 84 "\ Y E LLO W TW IST AC IN 230 VAC ±5% F R O N T V IE W WIRING CHART: 230 - 253 VAC 60 Hz IN Use next lowest line input taps when operating full chassis or on 50 Hz. See User Guide for more information.
Page 88 HErtVY SLACK. AIRE -rU 1 14 w j „ GROyNOTRACE...
Page 92 Y W I R I N G FIG. 3...
Page 94 DIODE MOUNTING Band on top w*C8 #• ^4 © 1977 IMSAI MFG. CORP. SAN LEANDRO, CA. ASSEMBLY DIAGRAM ALL RIGHTS RESERVED WORLDWIDE PSC-U REV. 1 1/77 MADE IN U.S.A. © 1 9 7 6 IMS ASSOCIATES, INC. SAN LEANDRO, CA.
Page 96 POWER SUPPLY PS-28U User Guide Rev. 1 USER GUIDE The PS-28U User’s only option Is the selection of a trans former primary tap. The transformer provides primary taps which allow selection at AC input voltages ranging from 92 - 126.5 and 184 - 253 VAC at 50/60 Hz. As the PS-28U is an unregulated supply, the supply vol...
Page 98 Functional Description POWER SUPPLY FUNCTIONAL DESCRIPTION The IMSAI PS-28D Assembly is a modular unregulated power supply for the IMSAI 8080 System. It provides the basic unregulated +8, +16, and -16 system supply voltages. The PS-28D requires a 117 volt AC single-phase line input, and includes a line noise filter.
Page 99 PS-28D Theory of Operation THEORY OF OPERATION The PS-28D Assembly is an- unregulated power supply that pro vides the basic +8, +16, and -16 voltages for the 8080 sys tem. It is comprised of four major component assemblies: line filter, transformer, rectifiers, and filters. The line filter is a triple PI L-C filter designed to remove high frequency noise present on the AC line.
Page 100 „ C 8 <• ft < 2 C 8 « E W @ fc) 1977 IMSAI MFG. CORF. SAN LEANDRO, CA. ASSEMBLY DIAGRAM ALL RIGHTS RESERVED WORLDWI PSC-D REV. 1 1/77 MADE IN U.S.A. (c, 1976 IMS ASSOCIATES, INC. SAN LEANDRO, CA.
Page 102 I M S A I 8 0 8 0 O v e r v ie w o f C h assis, E X P - 2 2 a n d P S -2 8...
Page 104 YELLOW ORANGE FIGURE 1 PS-28D OVERALL...
Page 106 FIGURE 2 WIRING DIAGRAM...
Page 108 ORANGE NO. 1 8 TERMS. 6&7...
Page 110 BOARD: PS-C IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS PART ITEM Solder 15-0000001 Heat Sink 16-0100006 Wakefield, 690-220-P (Modified) Screw 20-3402001 6-32x3/8” Phillips Pan Head CAD Machine Screw 6-32x3/4" Phillips Pan Head CAD Machine 20-3702001 Screw 20-4901001 8 - 3 2 x l V Binding Head CAD Machine Screw 20-5402000 10-32x3/8"...
Page 111 PS-28D Parts List IMSAI ITEM PART # QUANTITY DESCRIPTION/IDENTIFYING MARKS Hire 22-1018002 60" 18 AWG, Yellow, Gavitt 8522 Wire 12" 18 AWG, Twisted Pair, Yellow/Orange, 22-5018001 Stranded and Insulated Cord Line Cord, Beiden 17239 22-6000001 Bushing Strain Relief Bushing Grommet 24-0600001 Transformer 29-0100001...
Page 112 PS-28D Assembly Instructions General Unpack your board and check all parts against the parts lists enclosed in the package. Component Installation Insert and solder each of the two IK ohm, \ watt resis tors (brown/black/red) at locations Rl and R2 as shown on the Assembly Diagram.
Page 113 PS-28D Assembly Instructions Next connect a yellow and an orange #18 wire to terminal numbers 5 and 11 respectively. Twist and run the wires across the transformer to the anode pads of the CR4 and CR7. Solder. Temporarily install the transformer with h " hardware. Terminals 1, 2, 3 and 4 should face towards the fuse end of the PSC board.
Page 114 PS-28D Assembly Instructions Install and bolt heat sink (and diodes) onto the PSC board. NOTE: The schematic of the PSC shows the CRO-CRl wire and the CR2-CR3 wire going to transformer terminals 7 and 9 respectively. While this configuration is acceptable, the configuration resulting from steps 15-17 provides for shorter lead lengths and should be adhered to whenever possible.
Page 118 C P - A Functional Description Revision l C P - A F U N C T I O N A L D E S C R I P T I O N T h e C P - A b o a r d is t h e o p e r a t o r ' s p a n e l f o r t h e I M S A I 8 0 8 0 Syst e m .
Page 119 For situations in which it is not desired to locate the operator's panel at the cabinet front (such as use of the IMSAI 8080 as a dedicated controller), the CP-A front panel may be inserted (via extender card) into any back plane slot.
Page 120 CP-A Theory of Operations Revision l T H E O R Y O F O P E R A T I O N S T h e C P - A f r o n t p a n e l a s s e m b l y p r o v i d e s m a c h i n e s t a t u s i n d i c a t o r s , u s e r c o n t r o l l e d s w i t c h e s , a n d c o n t r o l f u n c t i o n s to t h e IMSAI 8080 o p e r a t o r .
Page 121 CP-A Theory of Operations Revision If the switch is set to RUN, on the next falling edge of the Phase II clock, the RUN and X-READY lines are set high. If the switch is set to STOP, the high STOP value and the Phase II clock are NANDed (.U16) and this value NANDed with the DATA OUT 5 bit (fetch/status) and the PROCESSOR SYNC line.
Page 122 CP-A Theory of Operations Revision 1 function is identical to the P-READY line used by the memory and I/O boards. The X-READY line is reserved for use of the front panel to avoid conflicts of two gates driving the same backplane line). During each of these functions, the processor is permitted to execute an instruction, and then is stopped in the...
Page 123 CP-A Theory of Operations Revision 1 stops the processor during the fetch of the designated memory byte- Similarly, the DEPOSIT switch, when operated, produces a pulse from the DEPOSIT one-shot which is buffered to the MEMORY WRITE line on the backplane. The leading edge of this pulse also starts a second one-shot with a much longer period which puts the data from the data...
Page 124 CP-A Theory of Operations Revision 1 The STATUS WORD DISABLE line (SSWDSB, Pin 53 backplane) is gated to insure that no conflicts are created between the bi-directional bus drivers on the MPU and CP-A boards. This signal is controlled by the same gating , that places the high order address switch values on the data bus for a front panel (address hex FF) read.
Page 128 CP-A REV. 4...
Page 130 CP-A, Rev. 4 Parts List BOARD: CP-A IMSAI QÜANTITY DESCRIPTION/IDENTTRYING MARKS ITEM PART # Solder 15-0000001 10’ Thennalloy/§106B-14 Seat Sink 16-0100002 Screw 20-2203001 4x%" Slotted Hex Head, Self-Tapping, Type A Sheet Metal Screw 20-3203001 #6x% Self-Tapping Sheet Metal 6-32x5/16" Phillips Pan Head Machine Screw 20-3302001 Screw...
Page 131 CP-A, Rev. 4 Parts List IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM PART # Capacitor 32-2233070 33uF Tantalum Diode 35-1000006 Signal Diode/lM914 Light Emitting Diode/red 35-3000001 8T97 36-0089701 Hex Tri-State Buffer/N8T97B 7400 36-0740001 Quad 2 Input HAND/SN7400N 7402 36-0740201 Quad 2 Input NOR/SN7402N 7404 36-0740401 Hex Inverter/SN7404N...
Page 132 CP-A Rev. 4 Assembly Instructions C P - A Rev. A S S E M B L Y I N S T R U C T I O N S U n p a c k y o u r b o a r d a n d c h e c k a l l p a r t s a g a i n s t t h e p a r t s l i s t s e n c l o s e d i n t h e p a c k a g e .
Page 133 CP-A Rev. 4 Assembly Instructions .the bottom of the board. The cathode can be recognized by its proximity to the flat side on the base of the light emitting diode Insert and solder each of the forty-four red LED's at locations: LOO through L07 LAO through LAI5 LDO through LD7...
Page 134 CP-A Rev. 4 Assembly Instructions Insert and solder the one 7430 IC at location U21. Insert and solder one 74LS30 IC at location U9. Insert and solder each of the three 74107 IC's at locations 018, 019, and 022. Insert and solder each of the three 74123 IC's at locations 017, U20, and 023.
Page 135 CP-A Rev. 4 Assembly Instructions To install the regulator and heat sink first bend regulator leads at degree angles to a 7805 length which allows their insertion into the hole pattern of the CP-A board. Then place heat sink as shown in Assembly Diagram and insert regulator as described above.
Page 136 CP-A Rev. 4 Assembly Instructions When the entire row has been spaced accurately, the board should be turned over and a center switch should be soldered in place taking care that the board is not bowed towards or away from the switches. When the board is positioned correctly, there will be a small space approximately 3/64 inch or slightly under 1/16 inch between the bottom of the switch...
Page 137 CP-A Rev. 4 Assembly Instructions Both the Photographic mask and the paper backup sheet should be trimmed to size after . assembly. Marks are. provided on both, and they should be cut out carefully using a straight edge and a very sharp knife against a wooden cutting board.
Page 138 IMSAI 8080.
Page 139 CP-A User Guide Revision 1 positions are not indicated on the indicator lights until the information is deposited in memory. At that time the information from these switches appears on the data bus. The high order byte of address switches is labeled ADDRESS-PROGRAMMED INPUT and these switches can be read bv the program as input port position hex FP or octal 377.
Page 140 CP-A User Guide Revision 1 The front panel must be holding the processor in the stopped condition for the SINGLE STEP switch, the DEPOSIT/DEPOSIT NEXT switch, or the EXAMINE/EXAMINE NEXT switch to operate. The EXAMINE/EXAMINE NEXT switch provides the facility for observing what is stored in memory in any location or for setting the program counter to any desired location to initialize program execution there.
Page 141 CP-A User Guide Revision 1 The DEPOSIT/DEPOSIT NEXT switch is similar in its operation but provides for changing the data or program stored in the memory. When the switch is actuated to the DEPOSIT position, the values of the lower address byte switches, that is, bits 0 through 7 labeled Address- Data, are deposited into the address currently being indicated on the 16 address bus indicators.
Page 142 CP-A User Guide Revision 1 The RESET/EXTERNAL CLEAR switch provides the system reset functions. When depressed to the EXTERNAL CLEAR position the CLEAR signal is given to all external input/ output interface cards which are wired to be reset by this signal.
Page 143 CP-A User Guide Revision 1 For a more complete description of the functions of the status bits, reference should be made to the Intel 8080 Micro Computer Systems User's Manual. The INTER- RUPT ENABLED indicator is turned on whenever the interrupts are enabled into the 8080 processor by the INTERRUPT ENABLE INSTRUCTION.
Page 144 March 5,1977 CPA REV 4 MODIFICATION Modification to cause front panel to always come up in "stop" mode at power-up time. Cut (comp, side) U-22 pin 11 free. (U-22 pin 11 was connected to U-22 pin 4 (ground) by a heavy trace under the chip.) Connect (solder side) Ü-18 pin 13 to U-16 pins 11 and 12.
Page 146 ER R A TA FO R CPA A N D EARLIER REV-4 1. The following modification must be made to the CPA REV-4 or e a rlie r REV'S i f i t is to be used with the RAM-16, RAM-32 or RAM -65 memory boards. This change makes the signal on backplane line 71 (RUN) agree with the bus d efin itio n .
Page 148 ü . o h CP-A.BEV-4 -i» p i n UD's I 1 9 7 7 IM S M M f G , C O U R , S A N L E A N D H O , M C i E t N U . S A. A L U H W IS RESERVEN WORLDWIDE COMPONENT SIDE FIGURE 1...
Page 150 FIGURE 3 MODIFICATION TO CPA REV. 4 & EARLIER ECN 77-0039...
Page 152 OPTIONAL MODIFICATION OF CP-A REVISION 4 OR EARLIER CP-A BOARDS TO CHANGE POWER SWITCH TO WRITE PROTECT/UNPROTECT 'SWITCH FOR USE W ITH RAM 4A BOARDS. REMOVE CP-A FROM CHASSIS Remove AC leads from pads A & B on CP-A, route to miniature toggle switch (e.g., C&K type 7101) mounted in V hole (pro...
Page 153 OPTIONAL MODIFICATION OF C P- A (Continued) F ro m U 24 p i n 1 1 t o t h e p a d c o n n e c t e d t o p i n From the bottom terminal of the HOLD light (cut from 1 / 1 6 ”...
Page 154 R U N 220nhin P H O T S T A T U S O L D H L D A L E D ( H O L D )
Page 155 - - cv---- er...
Page 160 CP-A FRONT PANEL FOR REVISIONS 3 & 4 FOR USE WITH NON-IMSAI MEMORY BOARDS T h i s m o d i f i c a t i o n s h o u l d , be made t o your f r o n t p a n e l board u s i n g two a d d i t i o n a l s e c t i o n s o f t h e 7400 t h a t i s l o c a t e d d i r e c t l y above S - 2 and S - 3 .
Page 164 MPÜ-A Functional Description Revision 1 MPU-A FUNCTIONAL DESCRIPTION The MPU-A board is the processor board for the IMSAI 8080 Microcomputer System. It is designed using the 8080 micro processor chip. The bus arrangement and board connector has been chosen to be 100% compatible with the MITS Altair M8800 .
Page 165 MPU-A Theory of Operation Revision 1 THEORY OF OPERATION The IMSAI MPU-A board is structured around the 808ÖA microprocessor chip, and much of the MPU-A board is wired to support the 8080A device. The MPU-A board provides interfacing between the 8080A chip and the data and address busses, clock and synchronization signals, and the voltage regulation necessary for the 8080A and other chips.
Page 166 MPU-A Theory of Operation Revision 1 The CLOCK line on the back plane is driven from the TTL Phase II clock line through a delay so that the phase relation of the clock signal to the Phase II and Phase I back plane signals, is nearly identical to that produced by the MITS Altair 8800 system.
Page 168 MPU-A Rev. 4 Parts List IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM PART § 74LS00 Quad 2 Input NAND (Low Power Schottky)/ 36-0740002 SN74LS00N 74LS02 36-0740202 Quad 2 Input NOR (LPS)/SN74LS02N Hex Inverter/SN74LS04N 74LS04 36-0740402 7474 Dual D Flip Flop/SN7474N 36-0747401 7805 36-0780501 5V Positive Voltage Regulator/ MC7805CP...
Page 169 MPU-A Rev. 4 Parts List IMSAI DESCRIPTION/IDENTIFYING MARKS ITEM PART # QUANTITY Socket 23-0800004 40 Pin Solder Tail Socket Capacitor 32-2233070 33-25 Tantalum Capacitor Crystal 35-5000001 13.00 MHz Crystal Diode 1N751A Zener Diode 35-1000005 Screw 20-3402001 6-32x3/8” Phillips Pan Head Machine 21-3120001 6-32 Hex Nut Lockwasher...
Page 170 MPU-A REV 4...
Page 172 I l l I I I I I vi ' • O r-* g o O' O_c * m « N C J fN fN - ^ .f n C J CO... a c c & s t a £ ' c c o t - DATA BUS SOCKET 1 I 1 Ml I I —...
Page 174 Assembly Instructions Edition 1 MPU-A ASSEMBLY INSTRUCTIONS Unpack your board and check all parts against the parts lists enclosed in the package. If gold contacts on the edge connector appear to be corroded, use pencil eraser to remove any oxidation. NOTE: Do not use Scotchbright or any abrasive material as it will remove the...
Page 175 Assembly Instructions Edition 1 15) Insert and solder the 40 pin IC socket at location Ä7. not install 8080 at this time.) 16) Insert and solder the one 1N914 diode (CRl) as shown in-the Assembly Diagram. NOTE: Observe polarity as indicated on the b o a r d .
Page 176 Assembly Instructions Edition 1 Before Installing the 8080 Chip If possible, before plugging in the 8080A chip, the board should be inserted in a chassis, the power turned on, and the the voltage levels checked on the 40 pin socket. Pin 2 should be ground and pin 11 should be -5 volts.
Page 177 Edition 1 U SE R GUIDE The IMSAX MPU-A beard requires no jumpers or user options for its use. The board is ready.to function after con nection to the b ac k plana and the bi-directional b u s . The bi-directional bus lines are provided by a 16-con...
Page 180 RAM 4A BOARD FUNCTIONAL DESCRIPTION The IMS AI RAM 4A board provides up to 4K bytes of static random access memory. The board is implemented with 2102-style memory chips that each have the capacity to store 1024 words of one bit for each word.
Page 181 xneory or operation RAM 4A BOARD THEORY OF OPERATION The memory circuits used on the IMSAI RAM 4A memory board are 2102- style integrated circuits housed in sixteen pin DIP packages. Their organization is 1024 words, each of which is one bit wide. address inputs are used to select the desired word and there is a chip enable to select the chip.
Page 182 RAM 4A Theory of Operation by the other half of CIO, and the other half of C9 controls memory block 3. The individual status of these four flip/flops is indica ted by the desigated red light-emitting diodes located in the upper left hand corner of the board.
Page 183 four decoder at location D4 is the setting of the board select flip/flop, a section of the 74LS74 at location D2, which is used to select that board which puts data on the DATA IN (DI) bus when a data input FE command is issued so that the protect status can be read by the microprocessor.
Page 184 4 A— 4 REV. 2 r a m...
Page 186 9£6l® V S * n NI 30V W 9£/S f r - V frlAIVU Z ' A 3 U N O IlV N V n d X 3 d O d N O I103S 3 0 IH D d 3 S fl 33S aaiMaiyoMaaAuasad siHOid n v lAtVüOVia A19IAI3SSV ‘...
Page 188 RAM 4A Parts List RAM 4A BOARD: IMSAI ITEM PART f l QUANTITY DESCRIPTION/IDENTIFYING MARKS Solder Solder 15-0000001 10’ 3-Prong Heat Sink Heat Sink 16-0100003 6-Prong Thermalloy Heat Sink Heat Sink 16-0100004 6-32x5/16" Phillips Pan Head Machine Screw 20-3302001 6-32 Hex Nut 21-3120001 #6 Internal Star Lockwasher3 Lockwasher...
Page 189 RAM 4A Parts List IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM PART # (For IK) lKxl Organization Static Memory 2102 36-0210201 Chip/P2101AL4 (For 4K) Quad 2 Input NOR/DM7402N 7402 36-0740201 7404 Hex Inverter/7404-N 36-0740401 74LS20 Dual 4 Input NAND (Low Power Schottky)/ 36-0472002 SN74LS20N 7425...
Page 190 RAM 4A Assembly Instructions RAM 4A-4 Assembly Instructions Unpack your board and check all parts against the parts lists enclosed in the package. If gold contacts on the edge connector appear to be corroded, use pencil eraser to remove any oxidation. NOTE: Do not use Scotch- bright or any abrasive material as it will remove the gold plating.
Page 191 Assembly Instructions Insert and solder one 7430 at location D Insert and solder one 74LS157 at location D5. Insert and solder one 74LS139 at location D4. Insert and solder one 7432 at location Cl. Insert and solder each of the eight 2101 memory chips at locations A9 through A16 for IK HAM Board and each of the thirty-two memory chips at...
Page 192 RAM 4A Assembly Instructions The smallest heat sink is used near the bottom of the bpard, closest to the edge connector. Insert screw and lockwasher through the regulator and heat sink and tighten with the nut on the back side of the board. Repeat this procedure with the two remaining heat sinks and solder each of the regu...
Page 193 User Guide USER GUIDE Board Selection In memory read or memory write operation (as well as responding to the output or input commands of FE) the IMSAI RAH 4A memory board is designed to be selected as one out of a maximum poss ible of sixteen RAM 4A memory boards present on the b u s .
Page 194 RAM 4A User Guide 3 if the board is to be selected when the above bit is low. Pin 15 Pin 2 Place jumper between pins 15 and if the board is to be selected when this bit is high. Pin 16 Pin 1 Place jumper between pins 16 and...
Page 195 RAM 4A User Guide Software Write Protect IK blocks of memory m a y Be write protected or xmprotected with an OUT command to port FE*. Selection of memory Board and block is selected with the high->-order 6 Bits in the output data word.
Page 196 RAM 4A User Guide TABLE- - 3 STATUS READ Data r i s I Same as [ Address Bits J (Board AddressI l 1 2 Block 3 3 Block 2 l=Unprotected Block 1 =Protected Block 0 The Interrupt Request flip/flop is set By an attempt to write into a protected location.
Page 197 F IG U R E 2...
Page 198 RAM 4A User Guide If it is desired to prevent the Interrupt Request flip/flop from being set (e.g., to avoid conflict with status reads if interrupts are not being used), cut the flip/flop line between the two pads to the left of D2 on the solder side (see Figure 3). Wait Cycle Selection No wait cycle is required for the memory chips supplied with the RAM 4A board.
Page 199 RAM 4A User Guide Battery Backup Operation For operating your RAM 4A board with Battery backup, simply con nect your battery to the board at the location indicated on the Battery Hookup Diagram. The battery should deliver 3 to 5 volts DC and should supply 300 milliamps of current.
Page 200 RAM 4A User Guide This simple test program allows the operator to output protect and unprotect commands to the memory board under test when the memory board is addressed at location hex, by using the sense switches on the front panel (high address switches). The program resides in the first IK block of memory of the board that is actually under test.
Page 202 RAM 4A Board Tester The.4K board tester is at PROM location 0400H. The IK tester is at 0500H. TO USE: Jumper the board to be tested to respond to addresses FxxxH. Insert the board in an 8080 with CPU-A, CP-A and PROM containing the test routine.
Page 203 KAM 4A Board Tester INTERPRETATION OF ERRORS: Phase I simply verifies that every location in RAM will correctly preserve data. The procedure is: Write '00' in location F000. Read location F000 and ensure that it is '00'. Repeat 1-2 using values '01', ' 02*,..'OF• ' and ■10', ,11',..,FF'.
Page 204 RAM 4A Board Tester TRUE LOC. CONTENTS RESPONDS TO: Step 1: Write 00 into F000 F000, F001 F000 nothing F001 Step 2: Write 01 into F001 F000 F000, F001 nothing F001 F000, F001 Step 4097: Read F000, 0 0 0 expecting nothing - and detect an error.
Page 205 :DBUG IM SA I 8080 DEBUGGER 04/0S/76 *0400,04FF; 0400 F3 3E FE D3 FF 21 00 F0 A F 77 46 38 C2 56 04 3C 0410 C 2 09 04 23 B4 C2 03 04 3E FD D3 FF 21 00 F0 74"...
Page 206 Errata 2/4/77 RAM 4A-4 NOTE: The RAM 4A Chapter applies to both RAM 4A-4, Rev. 2 and RAM 4 A - 4 r Rev. 3.
Page 210 PROM-4, Rev. 3 ■rneory of Operation THEORY OF OPERATION The PROM—4 board provides up to 4K of addressable Read only-Memory, utilizing the Intel 8702-1702 PROM devices. The board contains 256 bytes of memory for each 8702-1702 chip installed. Address lines AO through A7 are run directly to all PROM positions to select one of the 256 internal byte positions, while address lines A through All are used to select and...
Page 211 64K memory space. Tri-state bus drivers and fully-de coupled on-card voltage regulators provide reliable plug in compatibility with the IMSAI 8080 (S100). The PROM-4 board provides sockets for 16 1702 or 8702 PROMs. The socket locations are marked for easy selec...
Page 212 PROM 4 -5 1 2 REV 3...
Page 214 PROM 4-4 REV. 3...
Page 216 Parts List 30ARD: PROM 4 IM S A I ITEM PART # QUANTI" DESCRIPTION/IDENTIFYING MARKS Solder 15-0000001 1 0 ’ Heat Sink Thermalloy Heat Sink/6106B-14 16-0100002 Screw 20-3402001 6-32x3/8" Phillips Pan Head Machine Screw 21-3120001 6-32 Hex Nut Lockwasher 21-3350001 #6 Internal Stair Lockwasher Header 23-0400001...
Page 218 PROM ' 4 Rev. 3 Assembly Instructions ASSEMBLY INSTRUCTIONS Unpack your board and check all parts against the parts list enclosed in the package. If gold contacts on the edge connector appear to be corroded, use pencil eraser to remove any oxi dation.
Page 219 PROM 4, Rev. 3 Assembly Instructions ( ) 12. Insert and solder the two 8T97's at locations and C7 as shown on the Assembly Diagram. ( ) 13. PROM 4-4: Insert and solder the 16 24-pin sockets at locations Al through A and Bl through B Insert the 1702A's (or 8702A's) into their appropriate locations.
Page 220 RfcÖt, 1 10.00 IM S ssociates ASSEMBLY DIAGRAM P R O M 4 R B / 3 2/76 •2/27/76...
Page 222 PROM-4, Rev. 3 User Guide USER GUIDE The PROM-4 board uses Intel 8702 or 1702 ROM chips which are structured 256 x bits so that the m n i m u m incre ment possible in memory space is 256 bytes or 1 8702- 1702 chip.
Page 223 PROM-4, Rev. 3 User Guide DELAY SELECTION SOCKET The delay jumper socket (C9) of thevPROM-4 board allows the selection of one of four possible memory read cycle delays. The available delay times are 1, 2, 3, or 4 machine cycles, which translates to 1000, 1500, 2000 and 2500 nanoseconds.
Page 224 Board Addressing An example jumper for the Address Block beginning with the:. Address-C hex: The board address select jumper location is C2. permits any one of the 16 possible 4K blocks of memory space to be jumpered to form the board enable. The jumper location accepts a standard 16 pin IC socket —...
Page 225 PROM-4, Rev. 3 User Guide used for write enable may be inserted into this lo cation should very frequent changes of address be de sired. For a board whose address is expected to re main the same, jumpers may be inserted directly on the board.
Page 228 LED's for a total of 32 on-board LED's. This feature can be used to provide program-controlled out put for dedicated processor applications of the IMSAI 8080 in which case this PIO board would be plugged in where the front panel would normally be mounted and a special photo...
Page 229 PIO 4, Rev. 2 Functional Description The +5 and ground pins on the input or output port con nectors can be used to provide 5 volt power at up to 200 or 300 milliamperes total from the full board. In addition, approximately 100 additional milliamperes of +5 volt power would be available for each 8212 input or output port which is not installed in the PIO 4 board.
Page 230 This is a tri-state output and is enabled only when the chip is selected by the one-of-four decoder. The DATA OUTPUT bus in the IMSAI 8080 goes directly to the four.8212 output ports. The second enable line on each of...
Page 231 PIO 4, Rev. 2 Theory of Operation The LED's on the output ports are driven through the current- limiting resistor to +5 volts, so that when the output bit is low the LED is on. This orientation was chosen because the 8212's have a greater ability to sink current than they do to source current.
Page 232 ©1975 IMS ASSOC. iNC ^7404- 1 0 1 C8 0 ^CIO «C ü PORTS 74L3Q 74L02 *7402*« SEREGT IMS ASSOCIATES INC. ASSEMBLY DIAGRAM PI0 4 -1 REV. 2 5/76 (c;1976...
Page 236 Output Input PIO 4 REV 2...
Page 238 PI0 4-1 REV 2...
Page 240 PXO 4, Rev. 2 Parts List BOARD: PIO 4 IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS PART # ITEM 10’ Solder 15-0000001 Thennalloy Heat Sink/6106B-14 Heat Sink 16-0100002 Screw 6-32x3/8" Phillips Pan Head Machine 20-3303001 21-3120001 6-32 Hex Nut »6 Internal Star Lockwasher Lockwasher 21-3350001 Header...
Page 242 PIO 4, Rev. 2 Assembly Instructions ASSEMBLY INSTRUCTIONS 1. Unpack your board and check all parts against the parts lists enclosed in the package. 2. If gold contacts on the edge connector appear to be corroded, use pencil eraser to remove any oxi dation.
Page 243 PIO 4, Rev. 2 Assembly Instructions 4 output or 4 input ports are being installed, they would normally be installed from left to right as the address of the output ports; for instance: address 0 for position A3 and address 3 for posi tion A4.
Page 244 PIO 4, Rev. 2 Assembly Instructions ( ) 15. Insert and solder the 3 16 pin solder tail sockets at locations B9 and C , to provide for addressing jumpers, and at location C2 to provide for priority interrupt jumpers. REGULATOR AND HEAT SINK INSTALLATION ( ) 16.
Page 246 PIO 4, Rev. 2 User Guide USER GUIDE The PIO 4 Board has four input ports and four output ports. Each port has an eight bit latch associated with it. These ports may be addressed in one of two different ways: First, addressed as an input/output port with input or output in...
Page 247 On the falling edge of the strobe lines the interrupt line will change from high to low. This can be jumpered to the IMSAI 8080 priority interrupt lines to create an interrupt to the processor, and/or it may be used as an indication that the processor has not yet read the latched data.
Page 248 PIO 4, Rev. 2 User Guide Each of the data input lines on the input ports is tied to +5 volts through a IK resistor so that unused lines will be read as high data level or true data level. As an alternative, two EIA type connectors, 25 pins each, may be connected by way of flat cable and the 3M flat cable system to the board, so that the.
Page 249 Position C2 on the PIO 4 board is the interrupt select jum per socket. Appearing at the pins of this socket are all eight of the priority interrupt lines for the IMSAI 8080, the four input interrupt lines and the four output interrupt lines of the PIO 4 board.
Page 250 PIO 4, Rev. 2 User Guide BOARD ADDRESS SELECTION JUMPER SOCKETS The board address is selected by jumpers or a DIP switch in locations C and B9. There are two cases for which this board may be jumpered: ) to respond to input/out- put instructions and ) to respond to memory access in...
Page 251 PIO 4, Rev. 2 User Guide are also selected on location B9 with jumpers. If, for instance, address bit is desired to be a when the board responds, then pins 4 and 13 would be jumpered together. If address bit A2 was desired to be a 1, then either pins 3 or 13 may be jumperd together, since 13 and 14 are tied to the common address selection input.
Page 254 Functional Description Revision O FUNCTIONAL DESCRIPTION The PI06 Board provides the IMSAI 8080 Microcomputer System with two sets of 24 parallel programmable I/O lines and the capability of extending its own standard I/O bus to peripheral devices. Each set of 24 parallel I/O lines is derived from Intel's 8255 programmable peripheral interface integrated circuit.
Page 255 PI06 Functional Description Revision Ö The board size is 4.7 inches by.10 inches with a 100 pin edge connector on the bottom, dual 50's on 0.125 inch cen ters. On the top of the board are two 50 pin edge connectors, dual 2 5 ’s on 0.10 inch centers and a 26 pin edge connector, dual 13's also on 0.10 inch centers.
Page 256 PI06 Theory of Operation Revision 0 THEORY OF OPERATION The PI06 Board is enabled by having its address (as jumpered in the Address Jumper Sockets) appear on the microprocessor address lines during an input or output instruction. When this occurs, the outputs of the Address Jumper Socket will all be high, causing the output of the 74LS30 at location C7 to be low which is the true state of the board enable signal "/BDENA".
Page 257 PI06 Theory of Operation Revision 0 Traces from the 8255 lines "PCO” and "PC3" are brought from each 8255 to the bottom of the board where they may be jumpered to inverters (to get the right polarity) and then jumpered to either the processor's "/INT"...
Page 258 Theory of Operation TABLE 1 SIGNAL DESCRIPTION J2 & J3 CONNECTORS Description Pin # Name GROUND Port B lines brought directly from 8255 to connector. Port C lines brought directly from 8255 to connector. Port A lines brought directly from 8255 to connector.
Page 259 P106 Theory of Operation TABLE 1 Name Description /HIADD "A2" through "A7" are decoded. "A2" (Cont.) and "A3" may be jumpered to "DON'T CARE". /RESET Buffered external clear signal from microprocessor front panel switch. DBIN Buffered "PDBIN” signal from micro processor.
Page 260 n u D Theory of Operation TABLE 2 Pin # Name Description Buffered status output signal from the microprocessor which indicates that the address bus contains the address of an input device and the input data should be placed on the data bus when "PDBIN" is active.
Page 265 3 a is n n : i ’A 3 H 9 0 i d '•1977'W A A IM FO .CO RP 8anLfc*fldro'C A,M *J«lnU.8A...
Page 267 PI06-3 Parts List IMSAI Item Part # Quantity Description/Identifying Marks Heat Sink 16-0100002 Thermalloy, 5 Prong/6106-B-14 Screw 20-3302001 6-32 x 5/15” Phillips Pan Head Machine 21-3120001 6-32 x V (OD) Lockwasher 21-3350001 #6 Internal Star Wire 22-0030001 Wire, Wire Wrap, 30 G A., Kynar, Blue Header - i 23-0400001 16 Pin...
Page 269 PI06-6 Parts List IMSAI Item Part # Description/Identifyinq Marks Quantity Thermalloy 5 Prong/6106-B-14 Heat Sink 16-0100002 Screw 20-3302001 6-32 x 5/16" Phillips Pan Head Machine 21-3120001 6-32 x (OD) Lockwasher 21-3350001 #6 Internal Star Wire 22-0030001 Wire, Wire Wrap, 30 G A., Kynar, Blue Header 23-0400001 16 Pin...
Page 271 PI06-M Parts List IMS AI Item Part i t Quantity Description/Identifying Marks Socket 23-0800004 40 Pin, Solder Tail Low-Profile IC Socket TIC 834002 8T97 36-0089701 Tri-State Buffer/N8T97B 8255 36-0825501 Programmable Peripheral Interface/C8255 I si 3 - 2 3...
Page 273 Assembly Instruction Unpack your board and check all parts against the parts list enclosed. If gold contacts on the edge connectors appear to be tarnished, vise pencil eraser to remove any oxidation. NOTE: Do not use Scotchbright or any abrasive material as it m ay re move the gold plating.
Page 274 PI06-6 Rev. 1 Assembly Instructions side of the board. Solder the 7805 leads. NOTE: Be sure to place in proper position to prevent shorting. Insert the two 8255's at this time into their proper sockets (one for PI06-3) at locations A1 and A8. Insert the 16 pin headers at this time at locations B7 and C6.
Page 275 PI06 User Guide Revision O .SER GUIDE The basic purpose of the PI06 Board is to provide the microprocessor with two programmable 24 line parallel I/O ports and to extend a fully buffered microprocessor I/O interface to a peripheral device. The address of the PI06 Board is jumpered using the "Address Jumper Select"...
Page 276 PI06 : User Guide Revision 0 as memory locations. For details on these techniques and the microprocessor I/O bus, the user is referred to Intel's u s e r ’s guide again and the microprocessor user's guide. The J4 connector has 26 pins and also accepts the 3M type flat cable edge connectors.
Page 277 FIG U R E ONE ADDRESS SELEC TIO N » ^>o--- — — — P > °— s_ L O C A T I O N © 1976 IMS AI MFG. CORP. SAN LEANDRO, CA.
Page 279 n u o uotrt V U I U C TOTAL ADDRESS SPACE ( I / O PORT NUMBERS) =16 FIGURE TWO ADDRESS SPACE SUMMARY © 1976 IMSAl MFG. CORP. SAN LEANDRO, CA. 3 - 31...
Page 283 Asynchronous mode and 56,000 baud in the Synchronous mode. The SIO Board may be jumper-selected to respond either to input and output instructions from the IMSAI 8080 System or to memory reference instructions for memory-mapped I/O. Operation of the board requires 16 I/O port or address locations, which are selected by address bits 0 through When the board i -s used with input and output instruc...
Page 284 8251 USARTS. This configuration permits breaking an existing RS232 line and inserting the IMSAI 8080 System between the ends so that the control signals pass straight through and the IMSAI 8080 System intercepts, processes, and retransmits the data.
Page 285 Edition 2 Plated through-holes eliminate the need for any circuit jumpers. All jumper options are provided in 16 pin dual in-line package patterns so that jumpers may h e installed on headers plugged into IC sockets for convenient and quick changing.
Page 286 SIO board control port. The bi directional bus is connected to the DATA IN and DATA OUT busses on the IMSAI 8080 back plane through 8216 b i directional bus driver chips. The board enable signal...
Page 287 Theory of Operation Edition 2 The 4 output bit3 of the control port on the SIO board are latched into the 74177 which is clocked b y a com bination of board enable and address b it 3 and the write strobe either from the processor or from the front panel.
Page 289 Mil ' < 2 J f \. 1 mm m “ ’ 'll’’ 4. , ' » J ! j « J ? 3 MS A ' . ' . C — R7— > ~ — -R6— 1 G > >...
Page 291 REV-3 {§ } 1 < ? 7 S IM5 A S SO t- IN C . A U J N N _ \ 'S 4 H O T ^ A » l (sO r > 5 A l l ’ > !&£ / P Q f w n m w tw g tasro »w«9a»N —...
Page 293 SIC 2-1 REV 3...
Page 295 Channel A Channel B SIO 2-2 REV. 3...
Page 297 SIO 2-1 Rev. 3 Paxts List BOARD: SIO 2 IMSAI ITEM PART # QUANTITY DESCRIPTION/IDENTIFYING MARKS 15-0000001 Solder Thermalloy/6106B-14 Heat Sink 16-0100002 6-32x3/8" Phillips Pan Head Machine Screw 20-3402001 6-32 Hex Nut 21-3120001 #6 Internal Star Lockwasher 21-3350001 Lockwasher 16 Pin IC Header Header 23-0400001 Socket...
Page 298 SIO 2-1 Rev. 3 Parts List IMS AI ITEM PART # QUANTITY DESCRIPTION/IDENTIFYING MARKS 7404 36-0740401 Hex Inverter/SN7404N 74LS04 36-0740402 Hex Inverter (LPS)/SN74LS04A 7408 36-0740801 Quad 2 Input AND/SN7408N 74LS08 36-0740802 Quad 2 Input AND (LPS)/SN74LS08N 7425 36-0742501 Dual 4 Input NOR with Strobe/SN7425N...
Page 299 SIO 2-2 Rev. 3 Parts List BOARD: SIO 2 IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM PART # 15-0000001 Solder Thermalloy /6106B-14 Heat Sink 16-0100002 6-32x3/8" Phillips Pan Head Machine Screw 20-3402001 6-32 Hex Nut 21-3120001 #6 Internal Star Lockwasher 21-3350001 Lockwasher 23-0400001 16 Pin IC Header Header...
Page 300 SIO 2-2 Rev. 3 Parts List IMSAI ITEM QUANTITY DESCRIPTION/IDENTIFYING MARKS PART # 7404 36-0740401 H ex Inverter/SN7404N 74LS04 36-0740402 Hex Inverter (LPS)/SN74LS04A 7408 36-0740801 Quad 2 Input AND/SN7408N 74LS08 36-0740802 Quad 2 Input AND (LPS)/SN74LS08N 7425 36-0742501 Dual 4 Input NOR with Strobe/SN7425N 74LS30 36-0743002 8 Input NAND (LPS)/SN74LS30N...
Page 301 SIOM-1 Parts List IMSAI PART # QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM 7408 36-0740801 Quad 2 Input AND/SN7408N 75188 36-7518801 RD 232 Driver/SN75188 75189 36-7518901 RS 232 Receiver/SN75189A 75452 Dual Peripheral Driver/SN75452BD 36-7545201 8251 36-0825101 Programmable Communication Interface/ C8251 Diode 35-1000006 1N914 Zener Diode Opto Isolator/4N25 Isolator 36-0042501...
Page 303 SIO Assembly Instructions Unpack your b oard and check all parts against the parts list enclosed in the package. If gold contacts on the edge connector appear to be corroded, use pencil eraser to remove any oxidation. NOTE: Do not use Scotchbright or any abrasive material as it will re...
Page 304 Assembly Instruction Insert and solder the one 74LS00 at locaiton D5. Insert and solder the one 74LSQ2 at location C 3 . Insert and solder the one 7404 at location A10. Insert and solder the three 74LS04's at locations D4, D 7 , and D l l .
Page 305 Assembly Instructions DISCRETE COMPONENT INSTALLATION Insert and solder the fourteen .1 uf dis k capacitors at locations Cll through C24 as shown on the Assembly Diagram. Insert and solder the four 33 uf tantalum capacitors at locations Cl through C4 as shown on the Assembly Diagram. NOTE: Observe polarity (+ to +) as shown on the board.
Page 306 T h e SIO Board also includes all logic necessary to control the 8251 devices from the IMSAI 8080 Back Plane. Fo r reference information on the programming and operation of the 8251 chip, the user should refer to the Intel 8080 Microcomputer Systems User's Manual.
Page 307 USER'S GUIDE REVISION 0 SIO BOARD ADDRESSING Address Bit Function C/ET on 8251 ' s 0 =* DATA 1 » CONTROL SELECT CHANNEL A SELECT SELECT CHANNEL B 1 = * SELECT SELECT CONTROL I / O 1 = » SELECT CARD ADORESS jumperaoie to any on«...
Page 308 SIO 2 Board Rev. 3 Users Guide Edition 2 for channel B control bytes would be hex 5 or octal 05. Address b i t 3 (A3) selects the board control I/O port. Whe n address b i t 3 (A3) is high, the control port will be enabled.
Page 309 S IO 2 USER'S GUIDE REVISION 1 SIO BOARD I/O PIN DEFINITIONS T T L LEVELS CURRENT LOOP RS232 LEVELS chassis ground Trans. Data Rec. Data Req. Send ® O r. to Send ® Data Set Rdy. signal ground Carrier Det. + •...
Page 310 R e v . 3 USER'S GUIDE RS 232 OPTION TRANSMIT DATA RECEIVE DATA REQUEST TO SEND CLEAR TO SEND < & DATA TERM. REAOY DATA SET READY Jumpen shown for connection as terminal or computer end LOCATIONS A3 CHANNEL A of an RS232 line.
Page 311 S IO 2 USER’ S GUIDE REVISION 1 RS232 INTERCHANNEL CONTROL JUMPERS and CARRIER DETECT T o receive carrier drtect ------------------ TERM. To originate carrier detect — ---------------- COMP.
Page 312 SIO 2 USER'S GUIDE REVISION 1 CURRENT LOOP CONNECTIONS WITH CURRENT SOURCE WITHOUT CURRENT SOURCE SIO BOARD ■M N — I Transmit Loop -OUT » ► __1 * • T Receive -OUT Loop ■ > 5 — - . 4...
Page 313 SIO 2 Board Rev. 3 Users Guide Edition 2 The TTL output levels are driven b y a 75452 dual peripheral driver, with open collector outputs, and a 220 o hm pull-up to +5 volts. The TTL data inputs drive 1TTL input, load and a IK pull-up to +5 volts.
Page 314 REVISION 1 RS232 INTERCHANNEL CONTROL JUMPERS and CARRIER DETECT FOR THROUGH CONNECTIONS FOR RS232 U N E DATA INTERCEPTION WITHOUT AFFECTING CONTROL SIGNALS TERM. T o receive carrier detect COMP. To originate carrier detect...
Page 315 SIO 2 Board Rev. 3 Users Guide Edition 2 Jumper CJ-A or CJ-B The jumper selection socket in A3 serves serial I/O channel A and the jumper selection socket in B8 serves serial I/O circuit B. Their functions are the same for their respec tive channels.
Page 316 USER'S GUIDE REVISION 1 SIO INTERRUPT SELECT SOCKET SIO 232 CLOCKS JUMPER’ OPTIONS LOCATION 2-1S; 4-13 ORIGINATE CLOCK FOR ASYNC ] USE — r CLOCK r e c ie v e Program 825T for xl 6 for asynchronous operation, for synchronous.
Page 317 The interrupt line from channel A and channel B both appear on the interrupt select socket in position D3. All 8 of the IMSAI 8080 system priority interrupt lines on the back plane, also appear on the interrupt select socket.
Page 318 Revision 1 Jumper Location DJ, Located in Al The jumper select socket in Al provides facilities for originating and receiving clock signals for receive or transmit for use in the synchronous mode of communication. One-half of the socket controls lines for Channel A and the other half is dedicated to Channel B.
Page 319 Revision 1 B o a r d A d d re s s S e l e c t i o n Juntoe r S o c k e ts T h e b o a r d a d d r e s s s e l e c t e d b y ju m p e r s o r a D IP s w it c h...
Page 320 U s e r G u id e R e v i s i o n e i t h e r p i n s 3 a n d 1 4 m ay b e ju m p e r e d t o g e t h e r o r 3 an d 13 may b e ju m p e r e d t o g e t h e r ,...
Page 321 E d i t i o n Example Jumpers - To use the SIO Board in its simplest form, non-interrupted input/output instruction controlled, create jumpers as shown. A3 (88) 9 - 3 5...
Page 322 Sample sequence to set u p SIO for teletype and echo from keyboard to printer: Format used is 2 stop bits, parity, a nd 7 data bits. Reset IMSAI 8080 before running. Address and constants are in hexadecimal. LIST 3013...
Page 325 SIOC Board Rev. - 2 Functional Description SIOC BOARD FUNCTIONAL DESCRIPTION The IMSAI SIOC Board is a small optional board used with the Serial Interface (SIO Board). The SIOC provides user selection of any USART clock frequency from 15 Hz to 56 KHz. The generated clock frequency is determined b y a binary value set in two 16-pin jumper sockets.
Page 326 SIOC Board Rev. 2 Theory of Operation SIOC BOARD THEORY OF OPERATION The SIOC board is a modulo -N clock divider, where N is user selectable. The SIOC divides down the 2MHz 8080 02 clock to a rate appropriate for the 8251 USART devices.
Page 329 16 UN HEADER SOCKET 7430 7402 7493 16 PIN BOARO INTERCONNECT 7474 thru! .1 mF IK KW IMS ASSOCIATES, SCHEMATIC 01 AG SIOC REV 2 ©197«...
Page 331 SIOC Rev. 2 Parts List BOARD: SIOC IMS AI QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM PART # 15-0000001 5 ’ Solder #6 Fiber Washers Washers 21-3390001 6-32x3/4" Phillips Pain Head Machine Screw 20-3702001 21-3120001 #6 Hex Nut #6, 7/15" Spacer Spacer 21-3600002...
Page 332 SIOC Rev. 2 Assembly Instructions ASSEMBLY INSTRUCTIONS Unpack your board and check all parts against the parts list enclosed in the package. If gold contacts on the edge connector appear to be corroded, use pencil eraser to remove any oxidation. NOTE: Do not use Scotchbright or any abrasive material as it will remove the gold plating.
Page 333 SIOC Rev. 2 Assembly Instructions ASSEMBLY INSTRUCTIONS (cont.) TO MOUNT SIOC ONTO SIO BOARD The SIOC mounting is accomplished by placing the fiber washers into each of the three holes in the SIOC on the component side and each of the three holes in the SIO board on the circuit side.
Page 334 SIOC Board Kev. ^ Users Guide SIOC BOARD USERS GUIDE The SIOC board allows the selection of any USART clock rate between 15 Hz and 56 KHz, allowing data transfer rates of .23 baud to 56K baud. Designed to piggyback mount on the SIO board, the SIOC allows the user to select either the standard clock rates provided b y the SIO board or the user-generated SIOC rate.
Page 335 SIOC Board Rev. 2 Users Guide The binary divisor, N, can be determined by N = 1 2 x 106 Hz Clock This value should be converted to binary, and the jumpers (or switches) in A1 and A3 set so that the NÄND input for every bit that should be a 1 is connected to the output bit of the counter.
Page 336 SIOC Board Rev. 2 Users Guide Jumper socket A5 as: C han. B . Chan. A 1200 A SIOC OOTCLK...
Page 337 SIOC Board Rev. t Users Guide Decimal to binary number conversion: The simplest method to convert a number to binary is to divide it repeatedly by 2, recording the remainder for each step. To convert the value 1389^Q to binary. Value Value/2 R e m a i n d e r...
Page 338 110A 150A 2400S 300A CHANNEL B 4800S 600A 12 CHANNEL A 9600S 1200A SIOC 19,200S 2400A 38.400S 1200S ASYNCHRONOUS RATES INDICATED "A " ASSUME *16 CLOCK SELECTED IN 8251 4800A SYNCHRONOUS RATES INDICATED 8 Y ’T 9600A SOCKET POSITON A5 EXAMPLE SHOWING CHANNEL A SET TO 110 BAUD FOR A TELETYPE, AND CHANNEL B SET TO A N O N -S TA N D A R D RATE SET BY SIOC JUMPERS...
Page 343 R e v i s i o n PIC-8 FUNCTIONAL DESCRIPTION The PIC-8 Priority Interrupt-Programmable Clock board provides the IMSAI 8080 Microcomputer System an eight level Priority Interrupt capability and a software- controlled interval clock. The Priority Interrupt system utilizes the Intel 8214 Priority interrupt control unit and monitors the 8 Priority Interrupt lines on the 8080 back plane.
Page 344 t ' i e - ö Theory of Operation Revision 3 .PIC-8 THEORY OP OPERATION Program control of the PIC-8 board is done entirely through one output port location. The address of this output port is jumper-selected in-socket positions E4 and E5, and forms the input to the 8 input NAND gate (741s30) .
Page 345 PIC-8 Theory of Operation Revision 3 request so that the next time the clock line rises, the flip flop is again reset to request another interrupt. interrupt request from this circuit is jumper-connected to any one of the priority interrupt lines and is handled by the 8214 circuitry exactly the same as any other peripheral board requesting an interrupt through the back plane would Output bit 7 is used to drive the base of the transistor...
Page 347 co n pone N r si Di 1 MS ssociates ASSEMBLY DIAGRAM PIC 8 RB/ 3 2/76 2/27/76...
Page 349 PIC 8 REV. 3...
Page 351 PIC-8,. Rev. 3 Parts List BOARD: PIC-8 IMSAI QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM PART # Quad 2 Input NAND/SN7400N 7400 36-0740001 Quad 2 Input NOR (Low Power Schottky)/ 36-0740202 74LS02 SN7402N Hex Inverter (LPS)/SN74LS04N 74LS04 36-0740402 Triple 3 Input NAND/SN7410N 7410 36-0741001 8 Input NAND (LPSJ/SN74LS30N 36-0743002...
Page 352 PIC-8 Rev. Parts List IMSAI ITEM PART # QUANTITY DESCRIPTION/IDENTIFYING MARKS Capacitor 32-2233070 33-25 Tantalum Capacitor Screw 20-3402001 6-32x3/8" Phillips Pain Head Machine 21-3120001 6-32 Hex Nut Lockwasher 21-3350001 ■ : #6 Internal Star Lockwasher Solder 15-0000001...
Page 353 PIC 8 REV. 3 Assembly Instructions A S S E M B L Y I N S T R U C T I O N S Unpack your board and check all parts against the parts lists enclosed in the package. If gold contacts on the edge connector appear to be corroded, use pencil eraser to remove any oxidation.
Page 354 PIC 8 REV. 3 Assembly Instructions 16 pin IC sockets. Insert and solder each of the fifteen .1 uf disk capacitors C3 through C17. See Assembly Diagram for locations. Insert and solder each of the two 33uf tantalum capacitors Cl and C2.
Page 355 PIC-8 User Guide Revision 3 USER GUIDE Request for an interrupt appears at the PIC-8 board in the form of one of the eight priority interrupt request lines being pulled to a logic 0 level. The 8214 chip will recog nize that one or more interrupts are being requested and it will determine which multiple request has the highest priority.
Page 356 P I C - 8 User Guide Revision 3 W h e n i n t e r r u p t s a r e i n i t i a l l y e n a b l e d i n a s y s t e m , t h e c u r r e n t p r i o r i t y s t a t u s r e g i s t e r s h o u l d a l s o b e i n i t i a l i z e d t o i n s u r e t h a t t h e i n t e r r u p t g e n e r a t i n g s y s t e m w i l l...
Page 357 PIC-8 User Guide Revision 3 for any purpose, whether it is to select or change the selection of the interrupt interval desired, or whether it is to change the current priority status register, or to output a bit 7 to the special purpose circuitry supplied by the user.
Page 358 PIC-8 Board Board Addressing Revision 3 BOARD ADDRESSING Positions E4 and E5 contain the user-jumpered 16-pin address selection sockets. These jumpers allow the PIC-8 board to respond to any 1 of the 2 5 . 6 . possible I/O port addresses.
Page 359 Board Addressing Revision 3 Each, socket contains values of 4 lines and their complements. Socket E5 controls lines AO through A3. Socket E4 controls lines A4 through A 7 . If the user-selected address presents a 1 on an address line, that line should be directly connected to the NAND input via a short wire jumper on the socket header.
Page 360 PIC-8 User Guide Revision 3 PRIORITY SELECT FOR THE INTERVAL GENERATING CIRCUIT In position D2, the jumper socket permits the selection of the priority level at which the interrupts generated by the interval clock circuit will occur. The interrupt request level from the interval clock circuit appears on pin 4 of the jumper socket, and the eight available priority levels inputs appear on pins 9 through 16 of the jumper socket.
Page 361 PIC-8 User Guide Revision 3 A transistor is provided to permit bit 7 to drive small loads such as a speaker or relay, and space is provided on the end of the board for such a device to be mounted. Connections to the driving transistor are made through solder paths available at the top of the board.
Page 362 U C R I B o a r d Rev. F u n c t i o n a l D e s c r i p t i o n E dit i o n 2 U C R I BOARD F U N C T IO N A L D E S C R IP T IO N T h e S e p t e m b e r ,...
Page 363 UCRI B o a r d Rev. T h e o r y o f O p e r a t i o n E d i t i o n 2 TH E O R Y OF O P E R A T IO N T h e U C R I b o a r d d i r e c t i m p l e m e n t a t i o n...
Page 364 U C R I B o a r d Rev. 2 T h e o r y o f O p e r a t i o n > E d i t i o n 2 I c e a s e s , C 1 4 d i s c h a r g e s a n d...
Page 365 UCRI B o a r d Rev. 2 T h e o r y of O p e r a t i o n E d i t i o n t h i s o p e r a t i o n a l a m p l i f i e r w e r e t h e...
Page 366 A3a mon...
Page 367 I MS ssociates ASSEMBLY DIAGRAM UCRI REV. 2 3/76...
Page 368 UCRI B o a r d Rev. A s s e m b l y I n s t r u c t i o n s E d i t i o n 2 A S S E M B L Y IN S T R U C T IO N S B e g i n a s s e m b l y b y i n s e r t i n g...
Page 369 U C R I B o a r d Rev. U s e r G uide E d i t i o n 2 U S E R G U ID E T h e U C R I b o a r d u s e r s h o u l d r e f e r...
Page 370 U C R I B o a r d Rev. U s e r G u ide E d i t i o n 2 T h e t r a c e s p r e s e n t l y t h e b o a r d * a r e...
Page 371 U CRI B o a r d Rev. U s e r G u ide E d i t i o n 2 A l t e r n a t i v e l y , t h e s e c o n d m e t h o d m a y b e u s e d .
Page 372 R I B o a r d R e v . B o a r d A d d r e s s i n g E d i t i o n BOARD A D D R E S S IN G P o s i t i o n s B 7 a n d B9 c o n t a i n...
Page 373 U C R I B o a r d R e v . B o a r d A d d r e s s i n g E d i t i o n S o c k e t B 7 c o n t r o l s l i n e s A 8 t h r o u g h A l l...
Page 376 3900 74LS02 8T97 75LS75 74LS04 16 PIN DIP SOCKET 74LS30 470pF .47 mF PR D Y .005m F k ____ thru C12 -1mF 47pF 33m F .001 mF IN914 J2 thru J4 PHONG PLUGS 470K 14W Not used 470K%W 330K14W lOOK’...
Page 377 UCRI SO FTWARE, REV. F u n c t i o n a l D e s c r i p t i o n U C R I SOFTWARE F U N C T IO N A L D E S C R IP T IO N T h e U C R I D r i v e r 5 1 2 - b y t e...
Page 378 U C R I S O F T W A R E , REV. T h e o r y o f O p e r a t i o n T H E O R Y O F O P E R A T IO N T h e U C R I D r i v e r u s e s...
Page 379 U C R I SO F T W A R E , REV. U s e r G u i d e U S E R G U ID E T h e U C R I D r i v e r h a s b e e n a s s e m b l e d...
Page 380 U C R I S O F T W A R E , REV. U s e r G u i d e A t y p i c a l c a l l i n g s e q u e n c e w r i t e b l o c k e d r e c o r d...
Page 381 U C R I S O F T W A R E , REV. U s e r G u i d e W h i l e d a t a b e i n g w r i t t e n , t h e h i g h o r d e r...
Page 383 FAOO * * * * * * * * UC R I C AS SET TE I N T E R F A C E D R I V E R * * * * * * * * 0 0 0 0 FAOO 0 0 1 0 FAOO...
Page 384 FA32 5E FA 0 7 8 0 I N I T ; I F W R I T I N G , I N I T AUTO VOL CT F A 35 07 90 F A3 5 0 8 0 0 LOOPS T C : F A3 5 0 8 1 0...
Page 385 FA7F 1 3 3 0 «LO O P : COUNT DOWN F A 8 0 CA E FA 1 3 9 0 W T A IL E X I T LOOP I F NO MORE DATA F A 3 3 1 4 0 0 PUT NEXT BYTE F A 8 4...
Page 386 FADF 19-30 F ADF 1 9 9 0 READ H I T STANDARD BLOCK HEADER. FADF 2 0 0 0 FADF C5 2 0 1 0 READH: PUSH SAVE R E G IS T E R TO BE USED FAEO MV I C , 0 C W I L L COUNT N O N - S Y N C S...
Page 387 F B 32 2 5 3 0 THE NUM3ER OF M ACHINE CYCLES CONSUMED BY EACH F 3 3 2 2 5 9 0 IN S T R U C T I O N BELOW I S N O T E D . F 8 3 2 2 6 0 3 F B 3 2...
Page 388 F I F 3 1 8 0 F 3 9 0 9 FE 3 1 9 0 T IM P N LOOP U N T I L NEX T S I G N A L F B 9 3 3 2 0 0 B I T S D : A , 3 B I T...
Page 389 FBEA 3 7 3 0 T E S T READ R O U T I N E . READ BYTES FPOM TARE a n d D I S P L A Y 3 7 9 0 FBEA THEM U N T I L S T O P P E D . THE U S E SHOULD ADJUS T VOLUMF FBEA...
Page 390 ******** [JCRI CASSETTE INTERFAC 0000 0010 0020 27 JUL 76 REVISION 1 0030 0040 OFA003 0050 0060 I/O PORTS 0070 0030 UCRIP 0FCH ;UCRI 0090 FRCNP 0FFH ;FRONT o i o a 0110 TAPE INITIALIZATION PARAMS (WHEN WRITING DUMMY 0120 CHARS TO STABILIZE AUTOMATIC VOLUME CONTROL) 0130 0140 INCHR...
Page 391 0590 D, A SAVE TEMPORARILY 0600 AN I 0F0H ZERO LOW NIBBLE 0610 E , A SAVE HIGH BYTE OF 1ST ADDR 0620 A, D GET SWITCHES BACK 0630 ZERO HIGH NIBBLE 0640 EXIT EXIT IF COUNT IS ZERO 0650 SAVE COUNT OF 4K INC'S 0660 SWAP NIBBLES...
Page 392 1190 COUNT DOWN 1200 IMIT0 LOOP UNTIL COUNT EXHAUSTED 121C RESTORE SAVED REGISTERS... 1220 1230 1240 • 1250 ; HIT STANDARD CASSETTE RECORDER I/O DRIVER. 1260 1270 CRIOD: INSURE ACCURATE TIMING 1280 PUSH SAVE REGISTERS TO BE USED... 1290 PUSH 1300 PUT STATUS BYTE IN A 1310...
Page 393 1790 ;RESTORE A 1800 1810 ; 1820 ; WRITE HIT STANDARD BLOCK HEADER. 1830 ; 1840 WRITH: PUSH ;SAVE REGISTERS TO BE USED... 1850 PUSH 1860 MV I A-SYNCH ;GET SYNC CHAR 1870 B,NSYNC ;GET # OF SYNC CHARS TO OUT 1880 WRTH0: CALL WRITB...
Page 394 2390 ; WRITE BYTE IN A TO TAPE. 2400 2410 WRITB: PUSH ?SAVE REGISTERS TO BE USED... 2420 PUSH 2430 PUSH 2440 ;CLEAR CARRY (RESET STOP BIT) 2450 MV I B, BPC ;GET 3IT COUNT 2460 3ITS0: C,ZPL ;SET TIMER TO ZERO PULSE LENGTH 2470 ;CARRY HOLDS NEXT BIT TO OUTPUT 2480...
Page 395 2990 MV I E, 1 ?NOT LOOKING FOR A SYNC FLAG 3000 RESET: PUSH ;SAVE REGISTER 3010 7RESET A & CARRY 3020 B, A ;INITIALIZE BYTE HOLDER 3030 TRAPL: UCRIP ;WAIT FOR TRAILING PULSE... 3040 3050 TRAPL MV I 3060 GBIT0: ;INITIALIZE PULSE LENGTH COUNT 3070 LEDGE: UCRIP...
Page 396 3590 A,ERR6 CHECKSUM ERROR 3600 NOTE ERROR 3610 A80RT 3620 READY: CALL READR READ NEXT BYTE 3630 IS IT LOW CHECKSUM BYTE? 3640 READZ CONTINUE IF IT IS 3650 IS IT ZERO? 3560 CONTINUE IF IT IS READZ 3670 ■ A,E RR 6 CHECKSUM ERROR 3680 NOTE ERROR...
Page 397 U C R I - 1 S o f t w a r e E r r a t a S h e e t E R R A TA S H E E T U C R I - 1 SOFTWARE T h e a r r o w s...
Page 400: Table Of Contents
TABLE OF CONTENTS Functional Description MIO Specifications Theory of Operations Photograph Assembly Diagram Schematic Parts List Assembly Instructions User Guide Appendices A. Test Cassette Description B. MIOA Listing C. MIOB Listing D. Debugging Information E. Component Illustrations...
Page 402 raxu Functional Description FUNCTIONAL DESCRIPTION INPUT/OUTPUT VERSATILITY The MIO, Multiple Input Output Board, is designed to meet all Input/Output require ments of most 8080 System Users by pro viding the User with the following Input/ Output interfaces: 1. one Data Storage interface to a standard audio cassette recorder;...
Page 403 Functional Description normally appears. EXTERNAL CONNECTIONS External Interface Connections are made from the three 26-pin edge connectors at the top of. the board. These contain the signals necessary for two identical para llel interfaces, and a serial I/O inter face. The Current Loop or EIA options are normally configured to provide a stan...
Page 404 Functional Description - 3-. The-. Data output of the UART may be jumpered to an EIA Driver, a Current Loop Driver, or a TTL Driver. Similarly, the Data input of the UART may be jumpered to an EIA Receiver, a Current Loop Receiver, or a TTL Receiver.
Page 405 Functional Description edge, 3. positive level, and 4. neg ative level. It is also possible to continuously gate data, into the latch. 2. Use PIO Status Signals to generate Interrupts or to be simply ^mon itored by the Program via the Control Port.
Page 406 Functional Description The CRI Port writes Biphase Encoded Data to the tape. This can be used to generate Byte/Lancaster or Tarbell data formats. The Biphase encoding generates Byte/Lan caster data formats by sending alternating l's and 0's when a zero bit is to be recor ded.
Page 408 Specifications MIO SPECIFICATIONS Basic Configuration The MIO board uses four I/O ports and is available with the following I/O interfaces: Two parallel (PIO) ports One control (CTL) port One cassette recorder (CRI) port One serial (SIO) port There are three 26 pin edge connectors on the top of the board, two for the PIO ports and one for the SIO port.
Page 409 Specifications Data Ready (DR) is available at CRL IJA. Clear Data Ready (CDR) is available at the PIO connector. Data Strobe (STB) is available at the PIO connector. Input data is accepted from the PIO connector. Input Data Strobe (IDS) is jumper-selec table for positive or negative edge triggering, gating or disable.
Page 410 Theory of Operation THEORY OF OPERATION The M IO ,;Multiple Input/Output Board, contains all the logic required to implement two latched parallel input/output (PIO) ports, a serial I/O (SIO) port, a cassette recorder inter face (CRI) port and a port for the control of the other ports or external devices.
Page 411 Theory of. Operation The DS2 input (to complete selection on the 8212} is con trolled by bit 7 of the control register, thus providing the required multiplexing. Serial I/O Port The serial I/O port is implemented using a universal asyn chronous receiver/transmitter chip (UART).
Page 412 Theory of Operation Control Port The control register output consists of two 74LS175s; one of which is used to hold the four least significant bits of the data for use in the output jumper area and the other of which is used to hold the four most signifi cant bits for controlling the internal operation.
Page 413 Theory of Operation which is a digital form of the received data. Line 8 shows the output of the zero crossing one-shot detector as if it were never disabled. Line 9 shows the disable gate for this zero crossing detector. This is the out...
Page 414 Theory of Operation In the input data stream from the recorder, when the pre sent data bit is the same as the previous data bit, a se cond transition occurs at approximately the eigth clock cycle. Because the one-shot is disabled, this transition will not be detected.
Page 416 MIO Silk Screen Errata J5 (Direct Interrupt Jumper) is not shown. jumpers Jl Pin 4 and J1 Pin 73, as shown on the AP-44 Jumper example in the User Guide. The following signal names in the output Jumper Area have been interchanged. OlDR should read I1DR 02DR should read I2DR 01DA should read I1DA...
Page 418 NO TE: A U G A T PINS NO T SHOWN MIO REV 2...
Page 420 Parts List BOARD: MIO Rev. 2 IMS AI QUANTITY DESCRIPTION/IDENTIFYING MARKS PART # ITEM MIO Rav. 2 92-0000042 PC Board Quad 2 Input HAND (Low Power Schottky)/ 36-0740002 74LSOO SN74LS00N Hex Inverter, (LPS)/SN74LS04N 74LS04 36-0740402 Hex Inverter, Open Collector (LPS)/...
Page 421 Parts List IMS AI ITEM QUANTITY DESCRIPTION/IDENTIFYING MARKS PART # 74LS395 36-7439502 4 Bit Shift Register with 3 State Outputs/SN74LS395N 75188 36-7518801 RS232 Driver/SN75188N 75189 36-7518901 RS232 Receiver/SN75189N 7805 36-0780501 5V Positive Regulator/7805CU 78L12 36-0781202 Regulator/MC78L12CP 8212 36-0821201 Input-Output Port/PB8212D...
Page 422 Parts List IMS AI PART # QUANTITY DESCRIPTION/IDENTIFYING MARKS ITEM 330 Ohm, Watt/orange, orange, brown 30-3330362 Resistor 30-3220362 220 Ohm, Watt/red, red, brown Resistor 470 Ohm, Watt/yellow, violet, brown Resistor 30-3470362 470 Ohm, Watt/yellow, violet, brown Resistor 30-3470462 Resistor 30-4100362 IK Ohm, % Watt/brown, black, red 1.2K Ohm, ^ Watt/brown, red, red...
Page 424 ERRATA MIO REV.2 1/22/77 Board Assembly Modification to lengthen the pulse generated by the 8T20 for more reliable resetting öf U36: After the board is assembled, install a 10 picofarad disk capacitor between U34 pins 12 and 14. Cut leads to 1/8" and solder to U34 pins 12 and 14 on the solder side of the board as shown.
Page 426 Assembly Note: When installing socket pins for jumpers, heat should be applied long enough (e.g. 3 seconds rather than 1 second) to allow solder to wick through the board and form a fillet on the component side. (Alternately solder can be applied from the top side.) This provides greater support to the socket pins so they won’t bend during jumper installation.
Page 428: Assembly Instructions
Assembly Instructions ASSEMBLY INSTRUCTIONS 1. Unpack your board and check all parts against the parts list enclosed in the package. 2. If gold contacts on the edge connector appear to be corroded, use pencil eraser to remove any oxidation. NOTE: Do not use Scotchbright or any abrasive material as it will remove the gold plating.
Page 429 Assembly Instructions 12. Insert and solder the one 470 Ohm, h watt (yellow, violet, brown) resistor at location R8 as shown on the Assembly Diagram. IC INSTALLATION All Pin.l's are toward the lower right hand edge of the PC board and the 100 pin connector. The pads for Pin 1 are square.
Page 430 Assembly Instructions Insert and solder the two 74LS00s at locations U29 and U46 as shown on the Assembly Diagram. Insert and solder the one 74LS32 at location U30 as shown on the Assembly Diagram. Insert and solder the one 74LS153 at location U31 as shown on the Assembly Diagram.
Page 431 Assembly Instructions Insert and solder the four 16 pin sockets at locations 01, U2, U19 and U44 as shown on the Assembly Diagram. REGULATOR AND HEAT SINK INSTALLATION Before installing the heat sink and regulator, bend the 7805 regulator leads at 90 degree angles to facilitate mounting on the heat sink.
Page 432 MIO USER GUIDE...
Page 433 MIO User Guide Table of Contents General Introduction Address Selection Table 1 - Group Address Selection Table 2 - Internal Address Selection Control Port Table 3 - CRI and PIO Control Table 4 - PIO and SIO Status Selection 111.1 Input Jumper Area Table 5 - IJA Signal Definition 111.2...
Page 434 MIO User Guide Table of Contents (continued) VI.2 External Interface Connections VI.3 Initial Adjustments VI.4 CRI Recording and Reading Procedures VI. 5 • CRI Test Programs Peripheral Interfacing VII. 1 RS-232-C EIA Interfacing Table 12 - RS-232-C Signals VII.2 Serial Current Loop Interface Table 13 - ASR33 and KSR33 Connections VII.3 Parallel Interface...
Page 435: User Guide
user Guide GENERAL The MIO board gives the User the following capabilities: one serial I/O port two parallel I/O ports one cassette I/O port one control port NOTES ON THE USER GUIDE The information which is needed to set-up and use the MIO board is divided into two classes: 1) information which is common to all types of I/O ports used on the MIO board;...
Page 436 User Guide ORDER OF INSTALLATION To avoid having to continually enter the test programs from the front panel, it is adviseable to complete the CRI interface before going on to the SIO or PIO ports. The test cassette can then be used to load Test Programs for checking the other ports (see Appendix A for a description of the test cassette).
Page 437 Table 1. Group Address Selection IC Pins Address Bits Jumper 8, 9 7, 10 6, 11 5, 12 4/ 13 3, 14 2, 15 1, 16 INTERNAL ADDRESS JUMPER AREA Table 2 shows the possible combinations. All legal jumper combinations are shown. The comment column indicates the hardware (and software) compatability...
Page 438 User Guide TABLE 2 - Internal Address Selection Jumpers Inserted Port Port Comments (Pin Number) Numbers Referenced (8,9) IMSAI SIO CONT (3, 14) Processor Tech (8, 9) 3P+S CONT (1, 16) CONT (6, 11) (3, 14) CONT Altair SIO (6, 11) PIO - (1, 16) Use Parallel port...
Page 439 UbCi UUJ.UB THE CONTROL PORT The CONTROL PORT is a complete 8 bit Input/ Output Port used for internal and external control functions. The operation of the Control Port is easily understood if we separate its functions into two categories: 1)Input Functions; and 2) Output Functions.
Page 440 User Guide lines are active. The decoding for this function is shown in Table 4. Table 3 - Control of CRI and PIO VALUE CONT BIT Enable CRI Write Circuitry Disable CRI Write Circuitry Enable CRI Read Circuitry Disable CRI Read Circuitry Enable CRI Ready on each bit Enable CRI Ready on each byte Select PIO Port 2...
Page 441 raru User Guide III.l INPUT JUMPER AREA The INPUT JUMPER AREA is organized as shown in figure 2. Row A contains the 8 input bits of the Control Port. Rows B, C, and D contain three types of signals: 1) the status input sources;...
Page 442 User Guide ’ Table 5: Input Jumper Area Signal Definition Description Location Signal Name Data Input for Bits 0-7 AO thru A7 SIO thru SI7 SIO UART Overrun Error Determined by CNTL, see Table 4 SIOS /RRDY Logical Inversion of RRDY /TRDY Logical Inversion of TRDY TRDY...
Page 443 SOURCE DEFINITIONS The possible sources in ROWS B, C, and D are defined as follows. B0-B6 B0-B6 are status signals used for the SIO channel. Note that B l , (SIOS) is a logical OR'ing of PE, FE, and OE. If this signal is used, the Control Port output word allows the User to decode this signal to determine which error (PE,FE,or OE) occurred.
Page 444 User Guide NOTE T h e c o n f i g u r a t i o n n e e d e d f o r e a c h t y p e o f p o r t w i l l b e c o v e r e d i n t h e S I O , C R I ,...
Page 445 i i A V User Guide NOTE If the Current Loop Driver is not used, it should be jumpered to the Ground signal at pin 9 of the OUTPUT JUMPER AREA. Table 6 Output Jumper Area Signal Definitions PIN# DESCRIPTION SIGNAL NAME Control Register Bit 0 Control Register Bit 1...
Page 446 User Guide SIO PORT PROCEDURES The SIO Port is a full 8 bit serial input/ output port. It is used in conjunction with the Control Port, which in this case allows the User to 1) read selected status lines from the UART: and 2) read and write on exter nal I/O control lines.
Page 447 User Guide OUTPUT JUMPER AREA ln the OUTPUT JUMPER AREA: The serial data from the UART (U2-12) must be jumpered to the appropriate transmitter (EIA, TTL, or Current Loop). The output bits 0-3 of the Control Port must be jumpered to the appropriate type of transmitter EIA, TTL, or OC) to be used as external control signals.
Page 448 User Guide SIO CONFIGURATION JUMPER AREA The UART can be configured to transmit and receive a variety of character lengths and parity configurations. The SIO Configuration Jumper Area is used to hardwire the configuration desired. It provides +V (for a logic 1) on Row B and Ground (for a logic 0) on Row A for connection to the configuration inputs in Row Table 7 defines these inputs.
Page 449 User Guide SIO BAUD RATE SELECTION The Baud rate for the UART is formed by dividing down Phase II. This permits the User to select virtually any rate between 45.5 and 9600 baud. The division is accomplished by presetting a 12 bit counter and incrementing it to a value of 4084, at which time it is reloaded.
Page 450 User Guide IV. 2 ___ EXTERNAL INTERFACE CONNECTIONS EIA CONNECTIONS Table 9 gives the signal names for the SIO connections to the 26 p in edge connector and the corresponding EIA 25 pin connector number. Signals marked with an asterisk are standard RS232 definitions.
Page 451 User Guide Table 9 SIO CONNECTOR (J4) SIGNAL DEFINITION Signal Name MIO Edge Connector EIA Connector Chassis Ground AA* TTL Out 2 Transmit Data BA* Open Collector Out 3 Receive Data BB* TTL in 1 Request to Send CA* Current Loop in + Clear to Send CB* TTL Out 1 Data Set Ready CC*...
Page 452 User Guide CURRENT LOOP CONNECTIONS T h e C u r r e n t L o o p S i g n a l s a r e : 1) IN+ { J 4 - 8 ) 2) IN- (J4-22) 3} OUT+ (J4-20) 4) OUT- (J4-24).
Page 453 MJ.U User Guide SIO TEST 3 The board should b e jumpered to connect the SIO serial output to the SIO serial input for this test. The starting address is 3106 H. The Sense Switches are used to define any bits which should not be transmitted as part of this test.
Page 454 User Guide V ..PIO PORT PROCEDURES The two parallel I/O ports available on the MIO are both addressed with the same I/O address from the 8080. The ports are multiplexed using bit 7 of the Control Output word as discussed in Section III. The two ports operate identically and have identical external interfaces on J2 and J3.
Page 455 User Guide PIO- STATUS SIGNALS (cont.) PIOS - If any of the signals IDA or ODR goes high, PIOS will go high. The signal which occurred may be determined by using the Control Output Port bits 6 and 7 as shown in Table 4.
Page 456 User Guide PIO CONTROL SIGNALS (cont.) CODR - a Clear Output Data Ready Line for each port to set the ODR Lines active low. This signal is generated from the external device when it is ready to receive data. OSTB - a negative Strobe Line is provided from each parallel output port.
Page 457 User Guide Table 10 PIO CONNECTOR (J2 and J3) SIGNAL DEFINITION MIO E DG E CONNECTOR E IA CONNECTOR SIGNAL NAME Ground +16 Volts Output Data Bit 0 Input Data Bit 0 Output Data Bit 1 Input Data Bit 1 Output Data Bit 2 Input Data Bit 2 Output Data Bit 3...
Page 458 User Guide V . 3 ___ PIO TEST PROGRAMS There are three tests shown in Appendix B for the PIO. Test 1 (starting at address 3109 H) continuously reads the Sense Switches and outputs this value to both PIO Ports and to the Sense Lights. Test 2 con...
Page 459 User Guide B y t e / L a n c a s t e r F o r m a t s To support the Byte/Lancaster Format, the software tape handler in Appendix B must be used. The conversion of Biphase Data Formats into Byte/ Lancaster Formats is explained in the following dis...
Page 460 User Guide Setting up the CRI Port involves: 1. configuring the hardware jumpers; 2. making the external interface connections; and 3. running test programs to check out the operation of the port. VI .1 . . , HARDWARE JUMPERS INPUT JUMPER AREA In the INPUT JUMPER AREA: The status signal CRIS (D4) must be jumpered to the desired input bit of...
Page 461 E r r a t a 2 / 1 8 / 7 7 T h e t e s t c a s s e t t e s u p p l i e d w i t h y o u r M I O B o a r d h a s b e e n r e c o r d e d a t 800 b i t s p e r s e c o n d i n s t e a d...
Page 463 M I O E r r a t a 2 / 1 8 / 7 7 I t h a s c o m e to o u r a t t e n t i o n t h a t t o r e a d c a s s e t t e s o n a n M I O B o a r d t h a t h a v e b e e n w r i t t e n o n a T a r b e l l B o a r d , t h e p r e f e r r e d B i t R a t e...
Page 465 User Guide T a b l e 1 1 : S t a n d a r d B i t R a t e B I T P R E S E T H E X B I N A R Y V A L U E B Y B I T (MSB=7) R E P R .
Page 466 User Guide Initial Adjustments VI. 3 The adjustments required for operating consist of finding the proper volume settings for recording and reading back the data, and setting the inter face so that it reads and writes in the proper phase (using jumper 7 and 8 respectively in the External Address Jumper Area).
Page 467 User Guide 7. Rewind the tape and read the tape using the program from above and playback volume determined there. Use the Sense Lights to determine the best recording volume. 8. If the Sense Lights do not come on during step 7, insert Jumper 8 in the External Address Area (to reverse the recording phase) and repeat the above steps.
Page 468 User Guide To read the object program from Appendix B, load the Bootstrap Program contained in Appendix A. Use the read procedure as defined above with the following additions. 1. Start tape position is 3 minutes and 30 seconds into side 1 of the tape. 2.
Page 469 User Guide V I I ___ PERIPHERAL INTERFACING This section will define the jumper configura tions required to interface the MIO board with different types of peripherals. An example will be given for standard serial EIA interfaces, serial current loop interfaces (for teletypes) and a para llel interface.
Page 470 User Guide VII . 2 . . Serial Current Loop Interface The simplest current loop interface to a Teletype uses only the serial input and output data lines. Hence, only bits 1 and 0 of the Control Input are used to indicate transmitter and receiver status. Internal to the MIO, the following jumpers must be added.
Page 471 i/i-LU User Guide VII. 3 .. Parallel Interface The IMSAI Key-1 Keyboard provides an example of a parallel interface. The keyboard uses one PIO in put port with its associated handshake signals. The example shown in the illustration at the end of this section uses the processor interrupt request line to signal that an input character is ready, and the interrupt acknowledge to signal acceptance...
Page 473 VII. 4 JUMPER EXAMPLE ILLUSTRATIONS...
Page 475 TELETYPE B O A R D A D D R E S S JUMPERS. L E A V E O PEN T O PUT B O A R D A T B L O C K 0. © 1976 I MS A I MFQ. CORP. SAN LE AN DR O .
Page 477 A D M -3 9600 BAUD @ 1978 IMSAI MFG. CORP. EON 77-0011 2/77 SAN t EANDRO. CA.
Page 479 ” I N ' ' U I p— 1 • « « „ 0 • : : • J “ I f ) ’ > 6212 0212 OCi 0 0 * 0 J (J C 9 0 U C . . I 0 0212 0212 o rv B O...
Page 481 i T M & M l S r e M P P O L A R IT Y S E L E C T JUM PERS TAR BELL CASSETTE PER SECOND 800 BITS...
Page 489 DIR. JM P S , i f ; “ c b o o o o o o o i i_J <=« - e - c - t s d ) “ O U T 'J M P S . ! B O O O O O O O £...
Page 493: Appendices
M I O U s e r G u i d e A p p e n d i c e s...
Page 495: Test Cassette Description
APPENDIX A Test Cassette Description The Test Cassette contains the programs MIOA and MIOB (the listings of which appear in Appendix B and C, respectively) recorded in standard Tarbell Format at 1500 bits per second plus a sync stream. These programs contain all the test routines described in the User Guide, as well as software handlers for sync generation, block formation, and CRC generation and checking.
Page 497 M I O T E S T C A S S E T T E L O A D E R ; I/O PARAMETERS 0 040 ;CASSETTE PORT — 0043 ;CONTROL PORT 0 004 ;CASSETTE READY BIT 3 800 3800H 3 800 310040 SP,4000H 3 803 3E60...
Page 499: Mioa Listing
APPENDIX B, M IO A LISTING...
Page 501 PAGE 1 aiOft.PEN APPENDIX 3 MIO BOARD CRI INITIALIZATION PROGRAMS ADDRESS DEFINITIONS FOR MIO BOARD CONFIGURED ;AS DEFINED IN MIO USER GUIDE - SECTION 1.2 ECU 42H 0042 = 0041 = ■ EQU 41H 0043 = EQO 43H 0040 = EQU 40H EQU OFFH ;SENSE LIGHTS AND SWITCHES...
Page 502 PAGE 2 MIOA.PRN 4 TO 0 RESPECTIVELY. COMPARE RECEIVED CHAR WITH TRANSMITTED CHAR. DISPLAY OFEH IF DIFFERENT FOLLOWED BY TRANSMITTED CHAR AND RECEIVED CHAR. IN NORMAL OPERATION DISPLAY TRANSMITTED CHAR. 3103: LXI SP,STACK 3145 31C03S ;SET CONTROL 3148 AP XRA A 3149 D343 OUT CNT MVI C,0...
Page 503 MIOA.PRN PAGE 3 31A3 CASF31 JZ SOUTl MOV A,B 31A6 78 3 1A7 D342 OUT SIO ;CHAR OUT 31A9 C9 ;INPUT A CHAR WHEN READY. IF AH ERROR ;OCCURS , PUT ?E,CE,FE,RRDY,TRDY IN 4 TO 0. IS CNT ;SEE IF READY ON ERROR 3 IAA DB4 3 SINP: 31 AC E60A...
Page 504 PAGE 4 HIQA.PRN 3202 OC INR C JNZ DLA51 3203 C2FF31 3206 3C INR A JNZ PLA51 3207 C2FF31 3 20A C9 PUSH H ;TAKE 121 CYCLES 3 20B E5 DONE: 3 20C El POP H 3 20D S5 PUSH H 3 20E El POP H PUSH H...
Page 505 PAGE 5 MIOA.PRK 3251 C24S32 JHZ CRIWl ;SET PARAMATERS LXI H ,BUFR 3254 210036 ;256 BYTES 3257 1E00 MV I S , 0 3259 3E3F MV I A , 3 FH ; CIVE LIGHTS AN INITIAL VALUE 3253 D3FF OUT SSPT CALL WRIT DO THE WRITS 325D CD9E32.
Page 506 PAGE 6 MIOA. PEN' ;LOOP COUNT 3 2BA ID DCR E ;LOOP TIL DONE 3 233 C2B132 JNZ WRIT1 MOV A,B ;WRITE CRC BYTE 1 3 2BE 73 32SF CDC332 CALL WRBYT ; BYTE 2 MOV A,C 3 2C2 79 3 2C3 CDCB32 CALL WRBYT XRA A...
Page 507 MIOA.PRN PAGE 7 3323 CD6A33 CALL G3YT CRC BYTE 1 3326 CD8F33 CALL CRC FORK VALUE . . 3 329 CD6A33 CALL GBYT BYTE 2 3 32C CD8F33 CALL CRC FOR THE LAST TIME! 3 32F 79 MOV A,C SET FLAG 3330 30 - ORA 3 3331 C9...
Page 508 M IO A .P R N PAGE 8 »■GENERAL CRC ROUTINE. COMPUTE FOR ONE 3YTE 338F ES CRC: , PUSH H 3390 D5 PUSH D 3391 A8- XRA B 3392 67 MOV H,A 3393 07 3394 07 3395 07 3396 07 3397 AC XRA H 3398 6F...
Page 509: Miob Listing
APPENDIX C MIOB LISTING...
Page 511 MI03.PRN ? - aGE 1 APPENDIX C • MIO BOARD CRI INITIALISATION PROGRAMS ;ADDRESS DEFINITIONS FOR MIO BOARD CONFIGURED ; AS DEFINED IN MIO USER GUIDE - SECTION 1.2 EOO 423 0042 0041 = EQO 419 0 043 = EQU 43H 0040 - EQO 40K 00FF =...
Page 512 PAGE 2 MIOB.PRN IN CHI GET IT 3051 □B40 3053 77 MOV M,A ;STORE IT 3054 23 INX H JMP SOOT2 GET NEXT BYTE 3 055 C34A30 DUMP PROGRAM FOR FORMING TAPE FOR LATER RE30CT LXI H,8ASA 3058 210031 DUMP: 305B 3E10 MVI A,103 305D 0343...
Page 513: Debugging Information
APPENDIX D DEBUGGING INFORMATION...
Page 515 Debugging Information If the problem still persists, it will be necessary to use the MIO Schematic Drawing as a guide in trouble shooting. While it may seem very complex at first glance, it is much easier to understand once it has been broken down into FUNCTIONAL BLOCKS (e.g..
Page 516 Debugging Information The problem can usually be traced to: 1. a defective chip; 2. a solder cross or bad solder joint or 3. a misplaced or incorrectly oriented component. A BRIEF LIST OF PROBLEMS WITH SUGGESTED POINTS TO CHECK ARE GIVEN BELOW. NONE OF THE PORTS RESPOND Check the jumpering of the EXTERNAL ADDRESS JUMPER AREA.
Page 517 Debugging Information NO INPUT FROM EXTERNAL DEVICE TO SIO Check U 7 -2 0 , the UART Receive Data Line. If Data is not present here, carefully check the jumpering of the IJA and/or the IJA Re ceivers . If Data is present, check the SIO Configura tion Jumpers and check all Control Inputs to the UART U7 (especially U7-4, UART Read Enable).
Page 518 Debugging Information Check the CRI Rate Jumpers. Refer to the User Guide. Check to insure that Input Data appears at U25-2. If Data appears, check the operation of the shift registers at U24 anji U25. no Data appears, check the zero crossing detector at U34.
Page 519 Table 14 TEST PROGRAM ADDRESSING AND CONTROL SENSE SWITCHES ENTRY SENSE LIGHTS CONTROL TEST IN HEX DISPLAY SIO 1 3100 Output Character Input Character SIO 2 3103 SIO 3 3106 Transmit Bit Mask Error Code PIO 1 3109 Output Character Output Character PIO 2 310C...
Page 521 User Guide Figure 9 Jumper Settings for Test Programs Address Selection (II) External:___ Jumper, 2 address 40H to 43H Internal: Jumpers 1 and 6 Input Jumper Area (III.l) Interrupts are not used. Data input as follows: Bit 7 - REIA2 Bit 6 - RE I A3 Bit 5 - REIA4 Bit 4 - PIOS...
Page 524 '>...
Page 525: Component Illustrations
APPENDIX E C O M P O N E N T I L L U S T R A T I O N S...
Page 527 PIN 1 PIN 1 24 PIN l . C . 8212 PIN 1 14 PIN l . C . 7 4 LS 123 (o r 74123) 74L S 0 0 74LS32 74LS 153 7 4 L S 0 4 74LS51 7 4 L S 7 4 74LS155 74LS 05...
Page 529 C A P A C IT O f « n h b diode W 4742 ( c r i ) IN75JA (CR2) SILICON DIODE JN 9 7 4 (CR3} @ 1 9 7 6 IMS/ lEAt...
Page 531 1 6 PIN SOCKET SOCKETS @1976IMSAI MFG. CORP. SAN LEANDRO, CA.
Page 533 P IN 1 I . C . INSTALLATION INTO SOCKET @ 1976 I MS AI MFG. CORP. SAN LEANDRO, CA.
Page 535 6 PRONG 7805 5V POSITIVE VOLTAGE REGULATOR HEATSINK HEAT SINK & REGULATOR @1976 I MS AI MFG. CORP. - SAN LEANDRO, CA.
Page 539 IMSAI 8080 Self-Contained System Acknowledgement Revision 2 The IMSAI 8080 Monitor, Assembler, and Text Editor, supplied by IMSAI Manufacturing Corporation free of charge, is a modified version of software written by Microtec of Sunnyvale, California for Processor Technology of Berkeley, California who distributed the package free of charge.
Page 541 IMS AI 8080 SELF-CONTAINED SYSTEM OPERATING SYSTEM The IMSAI 8080 Self-Contained System is a software system designed to run on the IMSAI 8080 computer. Included in the package is an Executive to handle memory files, an Assembler, and a line oriented Editor.
Page 543 IMSAI 8080 Self-Contained System Operating System Revision 2 Executive Commands Kill current line CONTROL-X Enter data to memory ENTR Display memory data DUMP Create, assign or display file information FILE Execute a program EXEC Assemble a source file to object code...
Page 544 IMS AI 8080 Self-Contained System Operating System Revision 2 FILE /NAME/ AAAA This command is used to enter, examine or modify parameters of files created in the system. Up to six files can exist simultaneously with any one of the files "current".
Page 545 iMBAi. 8UHU S e l f - C o n t a i n e d S y s t e m O p e r a t i n g S y s t e m R e v i s i o n D E L T L I L 2 ---- D e l e t e l i n e ( s )
Page 546 I M S A I 8 0 8 0 S e l f - C o n t a i n e d S y s t e m O p e r a t i n g S y s t e m R e v i s i o n 2 Restrictions: A m a x i m u m o f...
Page 547 IMS AI 8080 Self-Contained System Text Editor Revision 2 T E X T E D I T O R E d i t o r The editor is a line oriented editor which enables the user to easily create program files in the system.
Page 548 IMS AI 8080 Self-Contained System Assembler Revision 2 ASSEMBLES When the Assembler is given control by the executive, it proceeds to translate the Symbolic 8080 Assembly Language (Source) program into 8080 machine (object) code. Assembler is a two pass assembler which operates on the "current"...
Page 549 Self-Contained System Assembler Revision 2 Statements Statements may contain either symbolic 8080 machine in structions or pseudo-ops. The structurecf such a state ment i s : NAME OPERATION OPERAND COMMENT The name-field, if present, must begin in assembler char- act er~pösxtTön one. The symbol in the name field can contain as many characters as the user wants;...
Page 550 IMSAI 8080 Self-Contained System Assembler Revision 2 a symbol in the name field is assigned a value which is contained in' the operand field of the EQU pseudo-of statement. Example: 0057 POTTS EQU 128 assigns the value 128 to the name POTTS.
Page 551 Self-Contained System Assembler Revision 2 Relative Symbolic Addressing If the name of a particular location is known, a nearby location may be specified using the known name and a numeric offset. Example: BEG+4 CALL $+48 BEG MOV C, 'B In this example the instruction JMP BEG refers to the MOV A,B instruction.
Page 552 IMSAI 8080 Self-Contained System Assembler Revision 2 Expressions An expression is a sequence of one or more symbols, constants or other expressions separated by the arithmetic operators plus or m i n u s . P A M +3 I SA B - 1A'+52 LOOP+32H—...
Page 553 Self-Contained System Assembler Revision 2 E Q U ----Equal Symbolic Value Format is label EQU expression where label is a symbol the value of which will be deter mined from the expression, and expression is an expression which when evaluated will be assigned t o t h e symbol given in the name field.
Page 554 IMSAI 8080 Self-Contained System Object Tape Format Revision 2 OBJECT TAPE FORMAT The IMSAI Self-Contained System is supplied on paper tape In a blocked hexadecimal format. The data on the tape is blocked into discrete records, each record con taining record length, record type, memory address and checksum information in addition to data.
Page 555 IMSAI 8080 Self-Contained System Object Tape Format Revision 2 Checksum. The checksum is the Frames 9+2* (Record negative of the sum of all 8 bit Length) to 9 + 2 * (Record bytes in the record since the record Length) +1 mark (":"} evaluated modulus 256.
Page 556 I M S A I a UHU Self-Contained System Saving and Restoring Programs Revision 2 SAVING AND RESTORING PROGRAMS While the system has no explicit provision for saving and restoring programs, it is possible to do so with an ASR style teletype.
Page 557 O C T R E V I S I O N - = “ SELF CONTA INED SYSTEM 0 0 0 0 0 0 0 0 C 3 A 0 0 0 I N I T A ; DEAD START ;...
Page 558 NOT RECOGNIZED BY R O U TIN E DELETE CURRENT L I N E CTRL X DELETE CHARACTER : ALL D IS P L A Y A B L E CHARACTERS BETWEEN BLANK 8 Z ANO THE ; ABOVE ARE RECOGNIZED BY THE READ R O U T IN E , A L L OTHERS ARE S K IP P E O OVER.
Page 559 R E T U R N W I T H Z E R O S E T I F F C T R L S E E N . ;GET STATUS 00E9 DB 0 3 t t y i n k ;INVERT STATUS OQEB 2F TTYDA...
Page 560 P C H L ; BE H E R E 0 1 3 8 T H I S ROU TIN E CHECKS TO SEE I F A BASE CHARACTER STRING EQUAL TO ANY OF THE STRINGS CONTAINED IN A TABLE P O IN T E D TO BY D , E .
Page 561 0 1 6 F C 2 6 C 0 1 ZBU1 0 1 7 2 T H I S ROUTINE CALLS ETRA TO O BTA IN IN P U T PARAMETER VALUES AND CALLS AN ERROR ROUTINE AN ERROR OCCURRED THAT R O U T IN E .
Page 562 01DC CDBD05 NORM CALL /N O R M A L IZ E A S C I I VALUE S8LK O l DF C D 0D 09 CALL / SCAN TO NEXT PARAMETER 0 1 E 2 /RETU RN 0 1E3 DO O I E 1 * 1 1 8 2 1 0 L X I 0 , A 8 U F + 9...
Page 563 T H I S S U B R O U T I N E C O N V E R T S A S C I I H E X D I G I T S I N T O B I N A R Y ;...
Page 564 T H IS ROU TIN E OUTPUTS CHARACTERS OF A S T R IN G ; U N T I L A CARRIAGE RETURN I S FOUND. 0 2 7 A B , M ; FETCH CHARACTER s c r n 0 2 7 8 3EOO A , 13...
Page 565 02 C 4 4 5 5 8 4 5 4 3 ■EXEC’ ; EXECUTE COMMAND 02 C8 2 1 0 1 EXEC ; COMMAND ADDRESS 1 E N TR ' ; ENTER COMMAND 0 2CA 4 5 4 E 5 4 5 2 ENTR 0 2CE 7 6 0 4 0 2 0 0...
Page 566 T H IS ROUTINE I N I T I A L I Z E S THE B E G IN N IN G OF F I L E AODRESS AND END OF F I L E ADORESS AS WELL AS THE F I L E AREA WHEN THE F I L E COMMAND I S...
Page 567 EOFP ; S E T END 0 3A8 2 2 2 B 1 0 SHLD A , L ; I S ADDRESS ZERO? 03AB 03AC 8 9 0 3A0 CAB 2 03 F I L 3 5 7 7 6 5 F I L 3 0 : MV I ;...
Page 568 0 9 1 7 C9 SEARCH THE F I L E DIRECTORY FOR THE F I L E WHOSE NAME IN F B U F . RETURN I F FOUND, ZERO IS O F F , H, L P O I N T ENTRY W HILE S EARCHING, ON ENTRY FOUND WITH ADDR...
Page 569 A N D C H E C K F O R E R R O R R E T U R N T H IS ROUTINE USED TO ENTER DATA VALUES INTO MEMORY. EACH VALUE ONE BYTE AND IS W R IT T EN IN HEXADECIMAL VALUES GREATER THAT 25 5 W IL L CAUSE CARRY TO 3E SET AND RETURN TO BE MADE TO C A LL IN G PROGRAM...
Page 570 09D 7 CDA205 CALL COMO 09DA D2F A0A INSR GET HERE NEW L I N E I S GREATER THAN MAXIMUM L I N E 0 ADD 23 I NX 09 DE C D 9 2 0 5 CALL LOOM ;...
Page 571 BOFP ; B E G I N F I L E ADORESS 0 5 5 2 F1N1 : LHCD 2 A 2 9 10 A , H ; RETURN TO MONITOR 0 5 5 5 0 5 5 6 F I L E E M P T Y .
Page 572 T H IS R O U T IN E USED TO LOAO FOUR CHARACTERS FROM ; MEMORY IN T O REGIS TE R S B ,M ; FETCH CHARACTER 0 5 9 2 l o o m I NX 0 5 9 3 C , M ;F E T C H CHARACTER 0 5 9 9...
Page 573 NOR 1: 05CJ STOM ; STORE VALUES 0 5C<* C99AQ5 05C7 CO e . o ^NORMALIZE VALUE 0 5C8 0 , C 05 C9 C , 3 0 5CA 98 05 C 3 0 6 3 0 M V I 8 , ' 0 ' NOR 1 05CD C 3 C 3 0 5...
Page 574 0 6 2 F e n d p r e v i o u s l i n e 0 6 3 0 I NX 0 6 3 1 I NX 0 6 3 2 C A 3 6 0 6 DEL 3 IN X 0 6 3 5...
Page 575 A S M2: . CALL PAS 2 0 6 0 9 C D 9 3 0 7 LX 1 ,OBUF ^OUTPUT BUFFER AOORESS 06 8C 2 1 3 2 1 0 06BF COC 5 0 6 AOUT ;OUT PUT L I N E CALL 06 C2 C 3 8 C 0 6 ASM1...
Page 576 ; ERROR I F NO BLANK 0 72F C 20 6 0 B OERR ; CHECK OPCOOE 0 7 3 2 C 3 6 5 0 A OPCD T H I S ROU TIN E C HECKS THE CHARACTER AFTER A LABEL FOR A BLANK OR A COLON .
Page 577 C D 8 9 0 2 CALL ^CONVERT FOR OUTPUT 0 7 9 9 B IN H + 3 07 9 C 23 I NX 0 7 9 0 3 A 9 2 1 0 ASPC ; FETCH PCCLOW) CALL ^CONVERT FOR OUTPUT' 07A0 C D 8 9 0 2...
Page 578 DO ORG PSEUDO -O P ;G E T NEW O R I G I N 0 8 0C 9 9 0 ORG2: CALL ASBL 0 8 OF 3A B 2 1 0 OBUF ; GET ERROR IN D IC A T O R ;...
Page 579 A , L 0 8 7 7 ; RST IN SR U C T IO N 0 8 7 8 C A 5 5 0 8 TY31 TY 3 2 ; ACCUMULATOR IN S TR U C TIO N 08 7B FA5 80 8 ;...
Page 580 0 8 E 1 CD990B T Y S 6 : CALL AS 6L ,-FETCH OPERAND 0 8 E 9 A , L 0 , H 08 E5 B Y T E CDEE08 ASTO 0 8 E 6 CALL ; STORE 2ND A , D 0 8 E 9 TYP1...
Page 581 9 9 9 2 0 9 3 1 'DB ' 0 9 3 3 0 9 3 9 0 9 3 5 0 9 3 6 9 9 5 3 >DS’ 0 9 3 8 0 9 3 9 093A 03 0 9 3 8 9 9 5 7 ' D W...
Page 582 09 A 9 09AA 9 9 9 3 5 8 ' O C X ' 09AO 09 AE 09 A F 9 9 9 1 9 9 ' DAD' 09 B 2 09 B 3 0 9 8 9 9 9 9 6 5 2 09 B 5 ' I NR' 09 B 8...
Page 583 • m * - 4 1 * —• in O' in in o in < 2 UJ < a * —• O' o o I — < in o • —4 < UJ 0. in a 2 < Q tu UJ <...
Page 584 0A7D ; A CHARACTER OPCODES 0A 7E C D 50 0 A CALL COPC 0 A 8 1 2 1 2 D 0 8 O P I : L X I H ,T Y P 1 ; TYPE 1 IN S TR U C TIO N S 0A8<»...
Page 585 OAF 8 2 A 9 2 1 0 0CN2 : LHLD A 5 PC ; FETCH PROGRAM COUNTER 0AF8 ; ADD I N BYTE COUNT OAFC 2 2 9 2 1 0 SHLD ASPC ; STORE PC OAFF ; WH ICH PASS? 0 8 0 0 ;...
Page 586 P R E D E F IN E R EGIS TE R VALUES T H I S TABLE 0 8 6 0 RTAB : ' A ' 0 8 6 1 0 8 6 2 ' 8 ' 0 8 6 3 0 8 6 4 0 8 6 5 0 B 66...
Page 587 SEND 0B 8L CA530C CHECK FOR OPERATORS C P I ; CHECK FOR PLUS 0BB7 FE2B A S C I 08 B9 CAC^OB • . i ; CHECK FOR MINUS 08BC FE2D C P I ASC2 08BE C2DA0B SIGN 0 8 C 1 3 2 9 9 1 0 ;...
Page 588 A , H 0 C 9 1 0 C 9 2 H, A 0C L 3 0C99. C 3 3 8 0 C ASC7 SLA8 0 C 9 7 C D 2 0 0 8 ALAS : CALL AVAL 0C9A CA280C ERRA 0C9D 0AA8 OC...
Page 589 STORE 3 BYTES OF ZERO IN OBJECT CODE TO PROVIDE FOR A PATCH. QCAD 3E 9F MV I A , ' O ' ;G E T IN D IC A TO R e r r o 08 UF ; STORE IN OUTPUT BUFFER OCAF 3 2 8 2 1 0 PAS I...
Page 590 H , 3 R T 0 0 1 9 2 1 0 C I O U X I ; GE T TABUE ADDRESS c u r s MV I 3 , N8 R ; GET NUMBER OF BREAKPOINTS 0 0 1 7 0 6 0 8 ;...
Page 591 HOLD +IO ;G E T L 0 - 3 Y T E OF PC 0 D 7 9 3AOA10 HOUT ; TYEP 0D7C C D3A 02 CALL 0O7F 2 1 3 8 0 0 LX I H,BMES ; TELL USER WHAT I T CALL SCRN 0D 8 2 C D 7A 02...
Page 592 1 0 9 8 ;NUMBER OF LABELS n o l a ; S I G N STORAGE FOR SCAN 1 0 9 9 s i g n 1 09A OPRD: ^OPERAND STORAGE 1 09C ;OPERAND FOUND IN D IC A T O R o p r i 10 9D t e m p...
Page 593 IMSAI 8080 Bootstrap Loader BOOTSTRAP LOADER The IMSAI Bootstrap Loader is a system that allows the user to get a general paper tape loader, into any region of RAM using only a 32-byte key-in. It requires an ASR33 teletype. To use this loader, proceed as follows: Key in the basic bootstrap given below starting,at location 0000.
Page 594 IMSAI 8080 B o o t s t r a p L o a d e r s u r e t o l o c a t e t h e l o a d e r i n a r e g i o n w h e r e...
Page 595 IMSAI 8030 B o o t s t r a p L o a d e r P r o g r a m L o g i c BOOTSTRAP LOADER PROGRAM LOGIC The Bootstrap Loader is a system that allows the user to read the Paper Tape Loader into the region of RAM that begins on a 256-word boundary using a specially formatted tape.
Page 596 x r i o r v o . u u u w Bootstrap Loader Program Logic Second Level Bootstrap: The second level bootstrap is a modified version of the Paper Tape Loader. The main differences between the two a r e : The second level bootstrap checksums itself to make sure it was loaded properly.
Page 597 IMSAI 8080 Paper Tape Loader PAPER TAPE LOADER The IMSAI Paper Tape Loader is a program that will load tapes in the standard object format (see appendix) from the paper tape reader on an ASR33 teletype. If the paper tape loader is ’ read in with the bootstrap loader (see Bootstrap Loader section), it will start itself up and print an "*"...
Page 598 Paper Tape Loader Program Logic PAPER TAPE LOADER PROGRAM LOGIC The IMSAI Paper Tape Loader is a program designed to load paper tapes in the standard object format from the paper tape reader on an ASR33 teletype. The loader is designed to use no stack or local RAM, thereby allowing it to be executed out of ROM.
Page 599 IMSAI 8080 Paper Tape Loader Program Logic Example: If memory locations 1 through 3 contain 53F8EC, the format of the hex file produced when these locations are punched is: :0300010053F8ECC5 Register Allocation: Since this loader uses no RAM, all variables and data are kept in the registers.
Page 601 BASIC KEY-IN BOOTSTRAP LOADER "" T H IS S IM P LE LOADER BOOTSTRAPS THE SECOND LEVEL BOOTSTRAP, WHICH TURN LOAD? THE REAL PAPER TAPE LOADER. TO USE T H IS LOADER, PROCEED AS FOLLOWS: ( I ) KEY I N T H IS LOADER, STARTING AT LOC 10 00 C 2 ) MOUNT THE BOOTSTRAP T A P E ,...
Page 602 SECOND LEVEL BOOTSTRAP T H I S LOADER I S PULLED BY THE B ASI C K E Y - I N LOADER. WHEN STARTED UP BY THE K E Y - I N LOADER, CHECKSUMS I T S E L F , TO MAKE SURE THAT I T HAS BEEN LOADED CORRECTLY, THEN PULLS I N AND...
Page 603 LOOP 1: MV I E , 0 ;CL EA R FLAG 0 0 6 9 1EB0 MV I C , 0 ; CLEAR CHECKSUM 0 0 6 3 OEOO ; GET S IO STATUS 00 6D DBQ 3 L 0 0 P 2 : 0 0 6 F AN I ;...
Page 604 00 D 4 B7 CHECKSUM. ZERO? 00D5 C A 6 9 0 0 LOOP1 ; Y E S , GO GET NEXT RECORD 00D8 LX I H ,S TA R T ; E LS E , GET RESTART ADDR 2 1 4 5 0 0 A , 1 3H OODB 3E13 STOP:...
Page 605 IMSAI PAPER TAPE LOADER REV 0 3 / 3 / 7 6 T H I S LOADER I S DESIGNED TO LOAD PAPER TAPES IN THE STANDARD OBJECT FORMAT CSEE THE SOFTWARE SECT ION OF THE 8 0 8 0 USER MANUAL) FROM AN ASR 33 TELETYPE-.
Page 606 FD31 DB 0 5 L00P2: ; GET S I O STATUS AN I FD33 E602 ; CHECK FOR CHARACTER L 0 0 P 2 FD35 CA31FD ; KEEP W A IT IN G FD38 7B A , E ; GET FLAG FD3 9 B 7 ;...
Page 607 FD9E CA9AFD STPL START FDA1 C500 FD J M P • PUT A DATA BYTE INTO CORE M ,0 FDA9 7 2 PUT-: ; STORE THE DATA ; INCREMENT THE H REG -FDA 5 23 I NX E , 8 5H ;R E S ET FLAG FOR NEXT DATA BYTE FDA 6 1E85 M V I...
Page 608 ' ■ " ‘ N...
Page 609 IMSAI8080 System User Manual Revision 1 APPENDIX - SCHEMATIC DIAGRAMS POWER SUPPLY MPU-A RAM 4 PROM 4 PIO 4 SIO 2 PIC -8...
Page 610 f f c C - L...
Page 611 95K uF 10K uF .1 uF Cl - thru .04 uF 500V C12 I CRO | thru j MR1121 CR3J MR501 thru CR7 i thru R1 ] 470 y2W SUPPLIED IMS ASSOCIATES INC. SCHEMATIC DIAGRAM REV. 1 5/76 £1976...
Page 612 C P ft-i-...
Page 613 DATA HEADER SOCKET «12 “ • 1 74LS04 utsj U» 741530 7404 «J10 741510 U 'l 7410 7402 U l» 7400 7427 U15.5 U17 * U1B ' Ul» u n ^ 7430 » T V ,U24 .OOlmF .OlmF 33mf 1NS14 LOO thru 107 LAO Omi L A »...
Page 615 > 8187 74LS04 821« ! > Swt C . Abo«« IMS A ssociates S C H E M A T IC D IA G R A » M P U - A REV 4 2/76 5 /1 8 /7 6...
Page 616 ( If t yf\'U...
Page 617 «M •1 • 2102 ■M 7412 • m ■ ] 74LS20 IS PIN JUftMEfl M CKrr 740* 14» 7401 3 n 1 c to j 74LS74 IT17 741513» m s m 7430 7404 74U18I H L ] .1 * » • 1 1M40O3 “...
Page 619 74LS02 7480 7474 74LS75 7490 03 J 7400 7410 7490 JUMPER SOCKET 74LS30 JUMPER SOCKET 7490 0 4 ] 74LS04 8214 JUMPER SOCKET 8T98 3 3 m f JhiF C3 thru C17 2N3904 R I. R3 thru BIS IKKW 220 KW ♦J I M S A ssociates...
Page 621 t io A1 thru AS 8212 C ? ] e 7 J B8 1 ! i. )4 s io j JUMPER SOCKET 7427 JUMPER SOCKET « 1 C 9 j JUMPER SOCKET 7402 C l thru C6 .Im F C9 thru C13 33m F C 8 j UQ thru U 7...
Page 622 I PJR1121 CR3J C R4 th ru MR501 ‘ th ru R 1 1 iK m R2 J 4 7 0 SUPPLIED IMS ASSO CIATES INC. S C H EM ATIC D IA G R A M REV. 1 5/76...
Page 623 »J10 w o* 74LS10 7410 0,3 1 7402 U l^ 7400 Ul 5.5 ”1 74123 U10 ~1 Ul« 74107 7430 j . l m F C11 thru C22 OOl m F .01 m f < * 1 3JmF CIO J 1N014 C h i UM thru U07...
Page 626 7490 7474 74LS75 7490 7400 7410 7490 JUMPER SOCKET 74LS30 JUMPER SOCKET 7490 74LS04 8214 JUMPER SOCKET 33mf f » n F C3 thru C17 2N3904 R1. R3thnjR1S IKKW 220 K M T Associates SCHEMATIC 0IAGRAM PIC 8 REV 3 2/76 2/27/76...
Page 627 A1 thru AS 8212 C 7 1 7 ^ ' . BIO] JUMPER S0CKE1 7427 JUMPER S0CKE1 7J.UirC‘0 JUMPER S0CKE1 7 4 LiSOC 7402 Cl thru CS C9 thru C13 L10 thru L17 L20 thru L27 L30 thru L37 LED'S L40 thru L47 R 1 1 IKXW...

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