Power Subsystem Description; Timing Subsystem Description - Alcatel 1850 TSS-320 Technical Handbook
Metro core transport service switch
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Also See for 1850 TSS-320:
- Technical handbook (276 pages) ,
- Commissioning handbook (108 pages)
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3.3.2.3 Loopbacks
For Test and maintenance purposes Loop-back capabilities, located on FERMAT Fpga, are supported.
For each STM16 Channel, FERMAT Fpga provides both "Line" side and "Equipment" side Loopbacks with
16xVC4 granularity (i.e. on the whole payload).
In both "Line side Loopback" and "Equipment side Loopback", the following operating modes are
supported:
•
"Loop and continue"
•
"Loop and send AIS"
These Loopbacks are controlled via ISPB bus.
3.3.3 Power subsystem description
Distributed power supply architecture on card is constituted by an input power stage and a set of compact
DC/DC converters.
The input power stage provides circuitry to:
•
monitor the presence of the battery A/B voltages after the input fuses
•
perform the OR-ing of the batteries
•
perform over-voltage and under-voltage protection on 48V power bus
•
control the inrush current at the start-up, plus the EMI filtering
The main unit power supply voltages will be obtained as follows:
•
2 isolated DC/DC converters (1/8 brick) to derive 3.3V and 1.2V operating voltages from the
48V back-plane bus
•
2 small non-isolated Step Down to obtain +2.5V, +1.8V from the +3.3V
An additional service voltage at 3.3VS, obtained from a duplicated 3.6V (V3A, V3B) coming from
backpanel, is used for on-board SPI circuitry: Remote Inventory device, status Leds, Goblin_4G and Kyra
Cpld.
3.3.4 Timing subsystem description
The clock management is carried out by EUCLIDE Asic, which performs the following main tasks:
•
synchronization to reference SDH Equipment Clock (SEC) T0, selecting between two clocks
at 38.88 MHz (coming from SLC/CRU cards)
•
feeding of the selected T0 clock (CK38) and related synchronism (MFSY) towards FERMAT
phase comparison to lock the on-board local 622.08 MHz VCXO to the selected T0 timing
reference (PLL at 622 MHz)
•
phase comparison, to derive the timing reference at 777.6 MHz for the 4G Backplane Frame
Format backpanel Links (PLL at 777.6 MHz)
•
feeding of T1 timing reference, derived by Rx Optical Line signal, towards SECs
Technical Handbook SDH
Units Description
Alcatel 1850 TSS-320 Rel.1.1
8DG 07734 CAAA Edition 01
47/84
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