Table 4-6 Reset Sources And Devices Affected; Figure 4-2 Reset Block Diagram - Motorola CPCI-6020 Installation And Use Manual

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Functional Description

There is an optional build configuration for reset from the RISCWatch JTAG interface. In Option

2, the RISCWatch CPURST_L will reset the Harrier ASIC in addition to the processor. This

option may be used in cases where the state of the Harrier logic must be guaranteed when a

RISCWatch CPURST_L is issued. However, implementing this option will prevent the use of the

RISCWatch probe Reset and Run from RAM mode since the Harrier SDRAM configuration

settings will be lost when the reset occurs. The Option 2 connection will not be implemented in

the standard board configuration.

Figure 4-2

Reset Block Diagram

FAL_L

PRST_L

RW_HRST_

RW_SRST_

RW_TRST_

The RST_ and PURST_ inputs of Harrier B are tied to those of Harrier A, respectively. The

AUXRST_ and RSTSW_ inputs of Harrier B are held inactive. The RSTOUT_, HRST0_ and

SRST0_ outputs of Harrier B are not connected. The watchdog timers of Harrier B do not

generate reset.

The following table shows which devices are affected by various reset sources: