Dual Harrier Assignments; Harrier Power-Up Configuration; Table 4-2 Harrier Power-Up Configuration Settings - Motorola CPCI-6020 Installation And Use Manual

Functional Description
Single channel DMA controller
Message passing unit supporting I2O and generic functions
Two internal 16550-type UARTs
2
Two I C Bus master interfaces
MPIC compliant interrupt controller
Four Xport channels for interfacing to flash or other external registers/devices
Refer to the Harrier Application Specific Integrated Circuit (ASIC) Programmer's Reference
Guide (ASICHRA1/PG) for additional information and programming details.
4.6.1

Dual Harrier Assignments

The CPCI-6020 employs dual Harrier ASICs identified as Harrier A and Harrier B. Harrier A is
used for access to part of system memory, access to all of flash memory, NVRAM, RTC,
external registers, UARTs, onboard I
interrupts. Harrier B is used for access to part of system memory, bridging to PCI Bus B and for
controlling some interrupts.
4.6.2

Harrier Power-Up Configuration

The Harrier ASIC XAD30-XAD0 pins provide configuration information for Harrier at power-up
reset time. The following table lists the default power-up reset state of these pins for the CPCI-
6020. The Select Option column indicates whether the power up setting can be changed by
build option resistor or by jumper, or if the setting is fixed and cannot be changed. The default
power-up setting column indicates the default values of the standard CPCI-6020 product.
Default settings for jumper options indicate power up value with jumper not installed.

Table 4-2 Harrier Power-Up Configuration Settings

Harrier
XAD Bus Select
Signal Option
XAD[30] Resistor
XAD[29] Fixed
XAD[28] Resistor
XAD[27] Resistor
XAD[26] Resistor
XAD[25] Fixed
XAD[24] Resistor
88
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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2
C, bridging to PCI Bus A and for top level control of all
Power Up
Default Register Bit(s)
0 XCSR.XPGC.HDM
0 XCSR.UCTL.UCOS
0 XCSR.BPCS.CSH
0 XCSR.BPCS.CSM
0 XCSR.BXCS.P0HO
/P1HO
1 XCSR.SDTC.SDER
A = 1 XCSR.GCSR.AOA
O
B = 0
Dual Harrier Assignments
Meaning of Power-Up
Default State
Xports not Hawk Data Mode compatible.
Select external clock source for UART.
Other PCI masters may access Harrier
configuration space.
All of Harrier's PCI configuration
registers are visible from PCI space.
Disable processor hold off at power up.
There are external buffers in series with
the BAx, RAx, WE, RAS or CAS signals.
Harrier A will respond to unmapped
address only cycles, Harrier B will not.