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NS32081-10 NS32081-15 Floating-Point Units
General Description
The NS32081 Floating-Point Unit functions as a slave proc-
essor in National Semiconductor's Series 32000
processor family It provides a high-speed floating-point in-
struction set for any Series 32000 family CPU while remain-
ing architecturally consistent with the full two-address archi-
tecture and powerful addressing modes of the Series 32000
micro-processor family
Block Diagram
TRI-STATE and Series 32000 are registered trademarks of National Semiconductor Corp
XMOS
TM
is a trademark of National Semiconductor Corp
C 1995 National Semiconductor Corporation
micro-
TL EE 5234
Features
Eight on-chip data registers
Y
32-bit and 64-bit operations
Y
Supports proposed IEEE standard for binary floating-
Y
point arithmetic Task P754
Directly compatible with NS32016
Y
NS32032 CPUs
High-speed XMOS
TM
technology
Y
Single 5V supply
Y
24-pin dual in-line package
Y
July 1988
NS32008 and
TL EE 5234 – 1
RRD-B30M105 Printed in U S A
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Table of Contents
Related Manuals for National Semiconductor NS32081-10
Summary of Contents for National Semiconductor NS32081-10
- Page 1 Single 5V supply 24-pin dual in-line package Block Diagram TL EE 5234 – 1 TRI-STATE and Series 32000 are registered trademarks of National Semiconductor Corp XMOS is a trademark of National Semiconductor Corp C 1995 National Semiconductor Corporation TL EE 5234...
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Page 2: Table Of Contents
Table of Contents 1 0 PRODUCT INTRODUCTION 3 0 FUNCTIONAL DESCRIPTION (Continued) 3 4 Bus Operation 1 1 Operand Formats 3 4 1 Bus Cycles 1 1 1 Normalized Numbers 3 4 2 Operand Transfer Sequences 1 1 2 Zero 1 1 3 Reserved Operands 3 5 Instruction Protocols 1 1 4 Integers... - Page 3 List of Illustrations Floating-Point Operand Formats Register Set The Floating-Point Status Register General Instruction Format Index Byte Format Displacement Encodings Floating-Point Instruction Formats Recommended Supply Connections Power-On Reset Requirements General Reset Timing System Connection Diagram Slave Processor Read Cycle Slave Processor Write Cycle FPU Protocol Status Word Format Dual-In-Line Package Timing Specification Standard (Signal Valid After Clock Edge)
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Page 4: Floating-Point Operand Formats
1 0 Product Introduction TABLE 1-2 Sample E Fields The NS32081 Floating-Point Unit (FPU) provides high speed floating-point operations for the Series 32000 family E Field F Field Represented Value and is fabricated using National high-speed XMOS technol- 0 75 ogy It operates as a slave processor for transparent expan- 1 50 sion of the Series 32000 CPU’s basic instruction set The... -
Page 5: Normalized Number Ranges
1 0 Product Introduction (Continued) TABLE 1-3 Normalized Number Ranges Single Precision Double Precision 127 c 1023 c Most Positive 3 40282346 1 7976931348623157 1022 Least Positive 1 17549436 2 2250738585072014 1022 Least Negative 1 17549436 2 2250738585072014 127 c 1023 c Most Negative 3 40282346... -
Page 6: 0 Architectural Description
2 0 Architectural Description (Continued) 10 Round toward positive infinity The nearest value which 100 Illegal Instruction Two undefined floating-point instruc- is greater than or equal to the exact result is returned tion forms are detected by the FPU as being illegal The binary formats causing this trap are 11 Round toward negative infinity The nearest value which is less than or equal to the exact result is returned... -
Page 7: 2 2 Addressing Modes
2 0 Architectural Description (Continued) and contains the opcode and up to two 5-bit General Ad- Memory Space Identical to Register Relative above ex- dressing Mode (Gen) fields Following the Basic Instruction cept that the register used is one of the dedicated CPU field is a set of optional extensions which may appear de- registers PC SP SB or FP These registers point to data pending on the instruction and the addressing modes se-... - Page 8 2 0 Architectural Description (Continued) TABLE 2-1 Series 32000 Family Addressing Modes Encoding Mode Assembler Syntax Effective Address REGISTER 00000 Register 0 R0 or F0 None Operand is in the specified register 00001 Register 1 R1 or F1 00010 Register 2 R2 or F2 00011 Register 3...
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Page 9: Floating-Point Instruction Formats
2 0 Architectural Description (Continued) 2 2 3 Floating-Point Instruction Set Movement and Conversion The NS32081 FPU instructions occupy formats 9 and 11 of The following instructions move the gen1 operand to the the Series 32000 Family instruction set ( Figure 2-6 ) A list gen2 operand leaving the gen1 operand intact of all Series 32000 family instruction formats is found in the applicable CPU data sheet... -
Page 10: 3 Traps
2 0 Architectural Description (Continued) Comparison 3 2 CLOCKING The Compare instruction compares two floating-point val- The NS32081 FPU requires a single-phase TTL clock input ues sending the result to the CPU PSR Z and N bits for use on its CLK pin (pin 14) When the FPU is connected to a as condition codes See Figure 3-7 The Z bit is set if the Series 32000 CPU the CLK signal is provided from the gen1 and gen2 operands are equal it is cleared otherwise... -
Page 11: 0 Functional Description (Continued)
3 0 Functional Description (Continued) pins ST0 and ST1 to keep track of the sequence (protocol) 3 5 INSTRUCTION PROTOCOLS established for the instruction being executed This is nec- 3 5 1 General Protocol Sequence essary in a virtual memory environment allowing the FPU to Slave Processor instructions have a three-byte Basic In- retry an aborted instruction struction field consisting of an ID byte followed by an Oper-... -
Page 12: 5 2 Floating-Point Protocols
3 0 Functional Description (Continued) Using the Addressing Mode fields within the Operation TABLE 3-1 General Instruction Protocol Word the CPU starts fetching operands and issuing them to Step Status Action the FPU To do so it references any Addressing Mode ex- CPU sends ID Byte tensions appended to the FPU instruction Since the CPU is CPU sends Operation Word... -
Page 13: 0 Device Specifications
Order Number NS32081N-10 or NS32081N-15 See NS Package Number N24A If Military Aerospace specified devices are required 4 2 ABSOLUTE MAXIMUM RATINGS please contact the National Semiconductor Sales Temperature Under Bias 0 C to 70 C Office Distributors for availability and specifications... -
Page 14: 4 Switching Characteristics
4 0 Device Specifications (Continued) 4 4 SWITCHING CHARACTERISTICS 4 4 1 Definitions All the Timing Specifications given in this section refer to 0 8V ABBREVIATIONS and 2 0V on all the input and output signals as illustrated in Leading Edge Rising Edge Figures 4 2 and 4 3 unless specifically stated otherwise Trailing Edge... - Page 15 4 0 Device Specifications (Continued) 4 4 2 Timing Tables 4 4 2 1 Output Signal Propagation Delays Maximum times assume capacitive loading of 100 pF NS32081-10 NS32081-15 Reference Units Name Figure Description Conditions Data Valid After SPC L E –...
- Page 16 4 0 Device Specifications (Continued) 4 4 3 Timing Diagrams TL EE 5234 – 19 TL EE 5234 – 20 FIGURE 4-4 Clock Timing FIGURE 4-5 Power-On Reset TL EE 5234 – 21 FIGURE 4-6 Non-Power-On Reset TL EE 5234 – 22 FIGURE 4-7 Read Cycle from FPU Note SPC pulse must be (nominally) 1 clock wide when writing into FPU TL EE 5234 –...
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Page 17: Spc Pulse From Fpu
4 0 Device Specifications (Continued) TL EE 5234– 24 FIGURE 4-9 SPC Pulse from FPU TL EE 5234 – 25 FIGURE 4-10 RST Release Timing Note The rising edge of RST must occur while CLK is high as shown Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (D) Order Number NS32081D-10 or NS32081D-15... - Page 18 National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation...