Digital Signal Processing (Front-End); Dvb-C Signal Broadcast Reception Block Diagram; Saw Filter; Channel Decoder Data - Philips 32PFL7403D/10 Service Manual

Circuit Descriptions, Abbreviation List, and IC Data Sheets
The application in this chassis is as follows:
2
• I C address 0x86.
• Down conversion from IF to low-IF frequency (5.166 MHz
centre frequency).
• Advanced filtering (for further rejection of adjacent
channels).
• Gain to obtain optimised channel decoder level. Control
signal is coming from channel decoder.

SAW filter

X6874D and X3451K
• Analogue sound for BG, I, DK, L, L'.
• DVB-T (digital reception sound and video).
For digital reception, the application in this chassis is as
follows:
• Rejection of adjacent channels.
• Switching is done by Master IF (3 inputs).
• One SAW covering both 7 and 8 MHz channels.
X6774D
• Analogue video for BG, I, DK, L, L'.
4MHz 4MHz
HPF HPF
Tuner Tuner
RF RF
TD1716_Mk4 TD1716_Mk4
C0h
X6874D X6874D X3451K X3451K
8MHz 8MHz 8MHz 7MHz 7MHz
36.13MHz 36.13MHz
36.125MHz 36.125MHz 36.125MHz
TDA9898 TDA9898
SIF AGC SIF AGC SIF AGC
RF AGC RF AGC
TOP TOP
PEAK AGC PEAK AGC
VIF AGC VIF AGC VIF AGC
L AGC L AGC L AGC
PLL PLL
Wideband AGC Wideband AGC
DIF DIF
IF IF
5,8MHz 5,8MHz
37.6MHz 37.6MHz
IF IF
IF AGC IF AGC
Side Band Side Band Band Pass Band Pass Band Pass
Filter Filter Filter Filter Filter
PLL PLL
T-AGC T-AGC
Sound Sound Sound Group Group Group
Nyquist Nyquist Nyquist
Trap Trap Trap Delay Delay Delay
Filter Filter Filter
Figure 9-4 DVB-C signal broadcast reception block diagram
Q528.2E LB
Channel decoder (TDA10048) DVB-T
The channel decoder has the following specifications:
2
• I C address 0x10.
• Decoding from low-IF to MPEG transport stream.
• During decoding: de-modulation, de-interleaving and error
correction.
• External clock buffer required.
• No start-up requirements.
• AGC monitor.
Channel decoder (TDA10023) DVB-C
The channel decoder has the following specifications:
2
• I C address 0x1C.
• Decoding from low-IF to MPEG transport stream.
• During decoding: de-modulation, de-interleaving and error
correction.
• External clock buffer required.
• No start-up requirements.
• AGC monitor.
9.3.2

Digital signal processing (front-end)

Refer to figure "9-4 DVB-C signal broadcast reception block
diagram" and "9-5 DVB-T signal broadcast reception block
diagram" for details of digital signal processing.
DVB-C DVB-C
PLL PLL
TDA10023 TDA10023
10-bit 10-bit TS TS
Decoding Decoding
ADC ADC interface interface
DVB-T DVB-T
PLL PLL
TDA10048 TDA10048
10-bit 10-bit TS TS
Decoding Decoding
ADC ADC interface interface
LIF LIF
SIF SIF
CVBS CVBS
9. EN 135
TS TS
I_17660_144.eps
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