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• S-METER SQUELCH
The S-meter signal is applied to the CPU from the meter
amplifier circuit (IC13a) via the SMAD line, and also the S-
meter squelch setting level is applied to the CPU. The CPU
compares these signals, then outputs a control signal to the
electronic volume control circuit (IC23) to cut out AF signals.
4-1-12 AUTOMATIC NOISE LIMITER CIRCUIT
The ANL (Automatic Noise Limiter) circuit (D62, Q44,
R381–R384) reduces pulse noises. The ANL function acti-
vates only when AM mode is selected.
The AM detector output signal from D63 is applied to the
cathode of D62 passing through R381 where it is divided by
R381 and R382. The signal is also applied to the anode of
D62, passing through R383 and R384.
When the ANL function is activated (Q44 is ON), C375 is
grounded. The detector output, including pulse noise, is
applied to the cathode of D62 only. If pulse noises are
received, the cathode voltage of D62 becomes higher than
the anode voltage and D62 turns OFF. Thus, while pulse
noises are received, the detected signal is not applied to the
AF switch(IC14).
• Automatic noise limiter circuit
AF signal
R383
from D63
C378
R381
R384
D62
R382
4-1-13 AGC CIRCUIT
The AGC (Auto Gain Control) circuit reduces IF amplifier
gain to keep the audio output at a constant level.
An RSSI signal is used for AGC function from the WFM IF
IC (IC7, pin 20) while in WFM mode, or used from the FM IF
IC (IC10, pin 12) while in FM, AM (except WFM) mode.
The RSSI output signal is amplified at the AGC amplifier
(Q33) during WFM operation. In other modes, the RSSI sig-
nal is amplified at the AGC amplifier (Q45), and passes
through the time constant circuit (Q46, Q47, R284, R290,
R291, C372, C373, C905) and is then applied to the IF
amplifiers (Q13, Q39). The AGC control signal is applied to
the VHF/UHF tunable bandpass filters after being amplified
at the VHF/UHF AGC amplifier (IC13b).
R375
Q44
+
ANL
to AF switch
C377
R385
IC14
AGC speed is controlled by changing the time constant at
the AGC control line with resistors (R284, R290, R291) and
capacitors (C372, C373, C905). R290 and C372 are used
for AGC slow, and R284 and C905 are used for AGC fast
mode's time constant. However, R291 and C373 are con-
nected to the AGC control line while scanning to obtain the
fastest AGC response.
4-1-14 S-METER CIRCUIT
The S-meter circuit indicates the relative received signal
strength while receiving and changes depending on the
received signal strength.
A portion of the AGC signal is applied to the meter amplifier
circuit (IC13a). The amplified signal is then applied to the
CPU (IC21, pins 64) as an SMAD signal to drive the S-
meter.
The SMAD signal is also used for noise and S-meter
squelch operation by comparison with the [SQUELCH] con-
trol setting level and received signal strength at the CPU.
4-2 PLL CIRCUITS
4-2-1 GENERAL
The PLL circuit provides stable oscillation of the 1st and 2nd
local frequencies. The PLL circuit consists of the PLL IC,
charge pump, loop filter and reference oscillator and
employs a pulse swallow counter.
4-2-2 1ST LO LOOP
The 1st LO circuit generates the 1st LO frequencies, and the
signals are applied to the 1st mixer circuit.
The generated signal from VCO 1 (Q14, Q15) or VCO 2
(Q18, Q19) is applied to the prescaler section in the PLL IC
(IC8, pin 8) after being amplified at the buffer amplifiers
(IC26, Q27). The applied signal is prescaled in the PLL IC
based on the divided ratio (N-data) to produce approx. 50
kHz signals which are applied to the phase detector section.
The generated reference signal from the reference oscillator
(X5; 12.8 MHz) is applied to the programmable divider sec-
tion in the PLL IC (IC8, pin 1). The applied signal is
prescaled in the PLL IC based on the divided ratio (1/256) to
produce approx. 50 kHz phase signals. The reference phase
signals are applied to the phase detector section.
The phase detector section compares 2 of the applied
phase signals. The phase detected signals are passed
through the charge pump section and then output from pin 4
of the PLL IC. The output signals are applied to the loop fil-
ter circuit (Q25, Q26) to be converted into DC voltage as a
PLL lock voltage. The lock voltage is applied to the CPU
(IC22, pin 61) via the buffer amplifer (Q24) as an L1AD sig-
nal to control the VHF/UHF tunable bandpass filter.
4 - 4
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