Pll Circuits - Icom IC-R100 Service Manual

4-2-8 SQUELCH CIRCUIT (MAIN UNIT)
The IC-R100 has 2 squelch systems, S-meter squelch and
noise squelch.
The noise squelch functions in FM mode. Some of the
noise components in the AF signal from IC1 are applied
to IC1 (pin 10) via a de-emphasis circuit (R17, C28, C29).
This de-emphasis circuit is an integrated circuit vvith
frequency characteristics of —6 dB/octave.
The active filter section in IC1 amplifies noise components
of frequencies of 20 kHz and above, and outputs the
resulting signals from pin 11. Output signals are rectified
by D2 and D3, and converted to DC voltage.
The rectified voltage triggers the squelch switch (Q3) and
then is applied to a squelch trigger circuit (IC1, pin 12).
The output level from IC1 (pin 14) becomes "LOW" and
turns ON D29. The AF signal is muted when the output
level from IC6(b) (pin 7) becomes "LOW."
The S-meter squelch functions in either AM or WFM
mode. The S-meter squelch signal from IC1 (pin 11) is
applied to IC6(a) through the squelch switch (Q3) to
compare with a reference voltage controlled by R86 on
the LOGIC UNIT. When this reference voltage level is
higher than .the S-meter squelch level from IC1 (pin 11),
028 is turned ON. The output level from IC6(b) (pin 7)
becomes "LOW" to mute an AF signal line.
When the S-meter squelch is in operation, Q19 is turned
ON to cut off the noise squelch.
4-2-9 AFC CIRCUIT (MAIN UNIT)
This circuit automatically controls the receive frequency
to compensate for the frequency drift in FM or AM mode.
IC2 is a monolithic IC which lights up "AFC" on the function
display when AFC function is in operation. A current
regulator (IC8) supplies a 10V reference voltage to
IC2 (pin 1) for comparison with the DC component in the
detected FM or AM signal.
The frequency drift selects an output signal to control
the receive frequency. The signal is output from IC2
(pin 6—8) and applied to the LOGIC UNIT.
4-2-10 AF AMP CIRCUIT (MAIN UNIT)
The de-modulated signals are applied to an AF mute circuit
consisting of IC5(b)~IC5(d) and then amplified at 015.
The amplified signals are applied to the [VOL] control
(R1) on the VR UNIT. When the squelch is closed, IC5
cuts off the AF signals like an AF mute switch. The AF
signals are power-amplified at an AF power amplifier
(IC7) to drive a speaker.
4-2-11 ANL CIRCUIT (MAIN UNIT)
This circuit eliminates the noise components to obtain
clear reception in AM mode.
4 一 4
The ANL circuit consists of В70--В73, 012, C69, and Q8.
The detector output from D10 and D11 is applied to the
anode of D12 through R72 and В73. The detector output
is also applied to the cathode of D12, passing through
R70 where it is divided by R70 and R71.
When the [AFC * ANL] switch is turned OFF, the anode
voltage of 012 is higher than the cathode voltage. 012
is therefore activated. However, when the [AFC * ANL]
switch is turned ON, the ANL signal line becomes "HIGH"
to turn ON 08. C69 and C117 are grounded. Therefore
the detector output, including pulses, is only applied
to the cathode of D12. The cathode voltage becomes
higher than the anode voltage and D12 shuts OFF just
at the moment when the pulses are received. The AF
signal (excluding pulses) then passes through D12 and
is applied to !С5(с).
* ANL CIRCUIT
Q8 069, R72 D10
AM
signal
[AFC-ANL]
switch
(LOGIC UNIT)
to
015
Fig. 6 AM5 line
4-3 PLL CIRCUITS
4-3-1 GENERAL (PLL UNIT)
The PLL circuit, using a one chip modulus prescaler (IC3),
directiy generates the 1st LO frequencies vvith 4 VCO's
on the TUNER UNIT. The modulus prescaler (IC3) sets
the dividing ratio based on serial data from the CPU,
and compares the phases of VCO signals and the
reference oscillator frequency. The PLL IC (IC3) detects
the out-of-step phase and outputs it from IC3 (pin 5).
A reference frequency is oscillated at X1.
4-3-2 REFERENCE OSCILLATOR CIRCUIT
(PLL UNIT)
A 12.6 MHz reference frequency is produced by the local
oscillator section of (СЗ and X1. C14 provides frequency
control.
4-3-3 LOOP FILTER CIRCUIT (PLL UNIT)
Phase-detected signals from !C3 (pin 5) are converted
to DC voltage by a loop filter consisting of an active filter
(Q2 and Q3).
The DC voltage (PLL lock voltage) is fed back to the
TUNER UNIT (EP2) through an LV signal line to control
the VCO oscillation frequency.
The unlock signal is output from (СЗ (pin 7).