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T
=
Pulse cycle (48MHz)
TBD
=
To Be Defined
(1
=
Access to the RAM
(2
=
Access to the register/latches
(3
=
For T = 48MHz
Asynchronous Motorola-Mode, Processor-Read-Timing
AB(10..0)
DB(7..0)
AS
R_W
XCS
XDSACK
(normal)
XDSACK
(early)
Asynchronous Motorola-Mode, Processor-Write-Timing
AB(10..0)
DB(7..0)
AS
R_W
XCS
XDSACK
(normal)
XDSACK
(early)
SPC3 Hardware Description
Copyright (C) Siemens AG 2003 All rights reserved.
SPC3
VALID
60
61
63
77
68
70
71
VALID
60
66
63
68
70
71
73
PROFIBUS Interface Center
62
Data Out
65
64
67
69
72
73
62
Data In
74
75
76
67
69
72
V1.3
66
E_Clock = log.'0'
78
79
E_Clock = log.'0'
Page 53
2003/04
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