Siemens SPC3 Hardware Description page 40

PROFIBUS Interface Center
XINT/MO MODE The SPC3 interface supports the following processors/microcontrollers.
1 1 Motorola microcontroller with the following characteristics:
synchron-ous
Motorola
The following can be connected:
The address decoder is switched off in the SPC3. The CS signal is fed to SPC3.
Condition:
1 0 Motorola microcontroller with the following characteristics:
asynchron-ous
Motorola
The following can be connected:
The address decoder is switched off in SPC3. The CS signal is fed into SPC3.
0 1 Intel microcontroller CPU basis is 80C51/52/32, microcontrollers from various
manufacturers:
synchron-ous
Intel
The following can be connected:
The address decoder is switched on in SPC3. The CS signal is generated for SPC3
internally.
0 1 Intel- and Siemens 16-/8-bit microcontroller families
asynchron.
Intel
The following can be connected:
Address decoder is switched off in SPC3. The CS signal is fed in to the SPC3.
Figure 7.1: Bus Interface
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2003/04
Synchronous (rigid) bus timing without evaluation of the XREADY signal
8-bit non-multiplexed bus: DB7..0, AB10..0
HC11 types: K, N, M, F1
HC16- und HC916 types with programmable E clock timing
All other HC11 types with a multiplexed bus must select addresses AB7..0 externally
from DB7..0 data.
For microcontrollers with chip select logic (K, F1, HC16, and HC916), the chip select
signals are programmable as regards the address range, the priority, the polarity, and
the window width in the write cycle or read cycle.
For microcontrollers without chip select logic (N and M), and others, an external chip
select logic is required. This means additional hardware and a fixed assignment.
The SPC3 output clock (CLKOUT2/4) must be four times larger than the E_CLOCK.
The SPC3 input clock (CLK) must be at least 10 times larger than the desired system
clock (E_Clock). The divider pin must be placed at „low" (divider 4), and it results in an
E_CLOCK of 3 MHz
Asychronous bus timing with evaluation of the XREADY signal
8-bit non-multiplexed bus: DB7..0, AB10..0
HC16 and HC916 types
All other HC11 types with a multiplexed bus must externally select addresses AB7..0
from data DB7..0.
Chip select logic is available and programmable in all microcontrollers.
Sychronous (rigid) bus timing without evaluation of the XREADY signal
8-bit multiplexed bus: ADB7..0
Microcontroller families from Intel, Siemens, and Philips, for example
The lower address bits AB7..0 are stored with the ALE signal in an internal address
latch. The internal CS decoder is activated in SPC3 that generates its own CS signal
from the AB10..0 addresses.
The internal address decoder is fixed wired, so that SPC3 must always be addressed
under the fixed addresses AB7..0 = 00000xxxb. SPC3 selects relevant address
window from the AB2..0 signals. In this mode, the CS-Pin (XCS) must be located at
VDD (high potential).
Asychronous bus timing with evaluation of the XREADY signal
8 bit non-multiplexed bus: DB7..0, AB10..0
Microcontroller families from Intel x86 and Siemens 80C16x, for example
External address decoding is always necessary.
External chip select logic if the microcontroller is not present
V1.3
SPC3
SPC3 Hardware Description
Copyright (C) Siemens AG 2003. All rights reserved.