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8.5.3 Timing in the Asynchronous Intel Mode (X86 Mode) :
In 80X86 operation, SPC3 acts like memory with ready logic. The access times depend on the type of
accesses.
The request for an access to SPC3 is generated from the negative edge of the read signal or the positive
edge of the write signal.
SPC3 generates the Ready signal synchronously to the fed in pulse. The Ready signal is reset when the
read signal or write signal is deactivated. The data bus is switched to the Tristate with XRD = 1.
No.
20
Address-Setuptime to RXD
21
XRD
to Data valid (Zugriff auf RAM)
XRD
to Data valid (Zugriff auf die Register)
22
Address (AB
) Holdtime after XRD or XWR
10..0
23
XCS
Setuptime to XRD
24
XRD-Puls-Width
25
Data Holdtime after XRD
26
Read/Write-Inactive-Time
27
XCS Holdtime after XRD
28
XRD/XWR
to XRDY
29
XRD/XWR
to XRDY
30
XREADY-Holdtime after XRD or XWR
31
Data Setuptime to XWR
32
Data Holdtime after XWR
33
XWR-Pulse-Width *
34
XRD, XWR Cycletime
35
last XRD
to XCS
36
XCS
to next XWR
37
XWR
to next XWR
Explanations:
T
=
Clock pulse cycle (48MHz)
TBD
=
to be defined
(1
=
Access to the RAM
(2
=
Access to the registers/latches
(3
=
For T = 48 MHz
SPC3 Hardware Description
Copyright (C) Siemens AG 2003 All rights reserved.
SPC3
Parameter
or XWR
or XWR
or XWR
(Normal Ready)
(Early Ready)
(XCS don't care)
PROFIBUS Interface Center
AMI-Vers.
Min
Max
0
4T+5
(88,3)
4T+18
(101,3)
0
- 5
6T – 10
(115)
2
6
10
0
4T + 5
5T+ 14
3T + 5
4T+ 14
4.3
12.8
10
10
4T
6T
4T + 10
2T + 10
6T
V1.3
ST-Vers.
Min
Max
Unit
0
3T+42.5
(105)
4T+20.2
(103,5)
0
-5
6T
10
(115)
3.1
10.2
10
0
5T + 16
4T + 12
6
22
10
10
4T
6T
4T + 10
2T + 10
6T
Page 49
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2003/04
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