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Refer to Section 3.4 for a description of the fairness algorithm which applies during SELECTION and RESE-
LECTION phases.
3.2.1
Selection overview
The SCSI device that won a normal arbitration has both the BSY and SEL signals asserted and has delayed at
least one bus clear delay plus a bus settle delay before ending the normal ARBITRATION phase.
The SCSI device that won QAS has the SEL signal asserted and has delayed at least one QAS arbitration
delay before ending the QAS phase.
The SCSI device that won the arbitration identifies itself as a SCSI initiator port by not asserting the I/O signal.
3.2.1.1
Selection using attention condition
3.2.1.1.1
Starting the SELECTION phase when using attention condition
The initiator shall set the Data Bus to a value that is the OR of its SCSI ID bit, the target's SCSI ID bit, and the
appropriate parity bit(s) [i.e., DB(P_CRCA) and/or DB(P1)]. The initiator shall create an attention condition
(indicating that a MESSAGE OUT phase is to follow the SELECTION phase).
If the arbitration was a normal arbitration, then the initiator shall wait at least two system deskew delays and
release the BSY signal. The initiator shall then wait at least one bus settle delay before attempting to detect an
assertion of the BSY signal from the target.
If QAS was used for arbitration then the SCSI initiator port shall wait at least one bus settle delay before
attempting to detect an assertion of the BSY signal from the SCSI target port.
The target shall detect that it is selected when the SEL signal and its SCSI ID bit are true and the BSY and I/O
signals are false for at least one bus settle delay. The selected target may examine the Data Bus in order to
determine the SCSI ID of the selecting initiator. The selected target shall then assert the BSY signal within one
selection abort time of its most recent detection of being selected; this is required for correct operation of the
selection timeout procedure.
The target shall not respond to a selection if bad parity is detected (see sections 3.9.2.1 and 3.9.3.1). Also, if
more or less than two SCSI ID bits are on the Data Bus, the target shall not respond to selection.
No less than two system deskew delays after the initiator detects the BSY signal is true, it shall release the
SEL signal and may change the Data Bus. The target shall wait until the SEL signal is false before asserting
the REQ signal to enter an information transfer phase.
3.2.1.1.2
Information unit transfers disabled
If information unit transfer agreement is not in effect for the connecting SCSI initiator port device, the SCSI tar-
get port shall follow the phase sequences defined in Section 3.11.
3.2.1.1.3
Information unit transfers enabled
If information unit transfers are enabled (see Section 4.3.12) for the connecting initiator, the target shall follow
the phase sequences defined in Section 3.5. On detecting the MESSAGE OUT phase, the initiator shall begin
a PPR (Parallel Protocol Request) negotiation (see Section 4.3.12 in this manual). On completion of the PPR
negotiation, the target shall proceed to a BUS FREE phase. If the first message received by the target during
the MESSAGE OUT phase is not a task management message or a PPR message, the target shall change to
a MESSAGE IN phase and issue a MESSAGE REJECT message followed by a WDTR message with TRANS-
FER WIDTH EXPONENT field set to 00h. If the target does not support the WDTR message, it shall follow the
MESSAGE REJECT message with an SDTR message with the REQ/ACK Offset field set to 00h.
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Parallel SCSI Interface Product Manual, Rev. A
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