Emif Control Registers; Sbsram; Sdram - Sundance Spas SMT332 User Manual

Version 1.3

EMIF Control Registers

The 'C6x01 contains several registers which control the operation of the
external memory interface (EMIF). Each memory space (CE0 to 3) has an
independent register, and in addition, there is a global control register.
A full description of these registers is within the 'C6x01 Peripherals Reference
Guide.
Briefly, these registers should contain the following values:
GC (global
control)
CE0
CE1
CE2
CE3

SBSRAM

Connected to the 'C6x01 external memory interface (EMI), using memory space
CE0, are 512k byte of zero wait state SRAM.
The SBSRAM can be set (via an internal 'C6x01 register) to operate at either the
'C6x01 core clock, or ½ the core clock speed. This requirement has to be considered
in conjunction with the 'C6x01 core speed and external memory speed refer to clock
speed for further details), but normally the SBSRAM would be set to run at the core
speed.

SDRAM

Connected to the 'C6x01 external memory interface, using memory space CE2, is a
16M byte bank of SDRAM.
The SDRAM operates at ½ the core clock speed.
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0x00003779
0x0000377D
0x00000040
0x8238C823
0x00000030
0x00000030 Defines SDRAM timings for access to
0xFFFF3F23
for access to FIFO flag programming.
For ½ speed SBSRAM
For full speed SBSRAM
Indicates SBSRAM
Defines async memory timings
Indicates SDRAM
the FIFO data.
Defines async memory timings
SMT332/372 User Manual