Block Diagram; Architecture Description - Sundance Spas SMT332 User Manual

Version 1.3

Block Diagram

Clock
Synth
TMS320C6201/
TMS320C6701
JTAG Port

Architecture Description

The SMT332 TIM consists of a Texas Instruments TMS320C6201 running at
200MHz and the SMT372 has a TMS320C6701 running at 166MHz. The TIM is
populated with 512k bytes of SBSRAM (synchronous burst SRAM) and 16M bytes of
SDRAM (synchronous DRAM) offering a total memory capacity of 16.5M bytes.
Additionally there are several programmable logic devices controlling such functions
as communications ports and global bus access.
256k bytes of in-circuit re-programmable Flash ROM is provided to store boot code.
J1 Primary Connector
0
Serial Port
DMA/FIFO
Comm-ports
1 2
J2 Secondary Connector
Page 6 of 36
3
J3 Global Connector
5 4
SMT332/372 User Manual
40
WAY
32Kx16 FIFO
32Kx16 FIFO
40
WAY
SBSRAM
512k bytes
SDRAM
16Mbytes
FLASH
256Kbytes
Global
Access
Logic
16
16