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Throughput Speed
Table B-1. Computer Configurations used with Relay Multiplexers
Computer
E1300/E1301 IBASIC
(Absolute Addressing)
(Select Code 8)
External Computer
(over GPIB to E1300/E1301
Mainframe
or E1405/E1406 Command
Module)
V/382 Embedded Computer
(C-Size system)
LADDR : logical address.
(LADDR * 64)
: multiply quantity, then convert to a hexadecimal number (e.g. 80 * 64)
16
When using DIAG:PEEK? and DIAG:POKE, the width (number of bits) is 8 or 16.
Appendix B
Throughput speed is based on the amount of command parsing and whether
the registers are accessed from the VXI backplane or from the GPIB. The
computer configurations which allow faster throughput relative to each
other are summarized below.
1. E1499A V/382 Controller with
(register access is from VXI backplane).
2. E1300/01 IBASIC absolute addressing with
(register access is from VXI backplane).
3. E1300/01 IBASIC select code 8 with
access is from VXI backplane).
4. External Computer using
(register access is over GPIB).
5. External Computer using
(register access is over GPIB).
Programming Method
READIO (-9826,Base_addr + offset)
WRITEIO -9826,Base_addr + offset;data
(positive select code = byte read or write
negative select code = word read or write)
READIO (8,Base_addr + reg number)
WRITEIO 8,Base_addr + reg number;data
VXI:READ? logical_address,offset
VXI:WRITE logical_address,offset,data
DIAG:PEEK? Base_addr + offset,width
DIAG:POKE Base_addr + offset,width,data
READIO (-16,Base_addr + offset)
WRITEIO -16,Base_addr + offset;data
(positive select code = byte read or write
negative select code = word read or write)
and
READIO
READIO
READIO
and
DIAG:PEEK?
DIAG:POKE
VXI:READ?
and
VXI:WRITE
Base Address
Base_addr = 1FC000
or
= 2,080,768 + (LADDR * 64)
offset = register offset (Figure B-1)
Base_addr = LADDR * 256
reg number = offset (Figure B-1)/2
logical address setting (LADDR)
offset = register offset (Figure B-1)
Base_addr = 1FC000
or
= 2,080,768 + (LADDR * 64)
offset = register offset (Figure B-1)
Base_addr = C000
or
= 49,152 + (LADDR * 64)
offset = register offset (Figure B-2)
= 1400
16
16-Channel Relay Multiplexer Registers
WRITEIO
and
WRITEIO
and
WRITEIO
(register
+ (LADDR * 64)
16
16
+ (LADDR * 64)
16
16
+ (LADDR *64)
16
16
.
16
79
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