Operation; Table 4-3 Bus Master Address Spaces - AMD Elan SC520 User Manual

4.3

OPERATION

There are three types of system bus masters supported on the ÉlanSC520 microcontroller:
the Am5
As shown in Table 4-3, each of the three bus masters can access specific types of address
space.
The Am5
space.
The PCI bus further specifies a separate space for device configuration registers.
The GP bus DMA controller supports fly-by transfers between GP bus devices and
SDRAM; therefore, as a bus master, it supports memory space only.
Table 4-3 Bus Master Address Spaces
Bus Master and
Address Space
CPU Memory
I/O
PCI Memory
Bus
I/O
1
Configuration
GP- Memory
DMA
Notes:
1. Accessed indirectly by the CPU via the PCI configuration registers in I/O space.
The Am5
(I/O space is limited to 64 Kbytes on the CPU). The PCI Local Bus Specification, Revision
2.2 further defines a separate space for configuration registers.
,
The ÉlanSC520 microcontroller divides these address spaces as follows:
Memory space
– ROM/Flash space for data and code storage using up to three chip selects (accessible
only by the CPU)
– SDRAM space for data and code storage
– GP bus memory space (accessible only by the CPU)
– PCI bus memory space (accessible only by the CPU and PCI bus masters)
– Internal memory-mapped configuration region (MMCR) registers (accessible only by
the CPU)
I/O space
– Integrated PC/AT-compatible peripherals (accessible only by the CPU)
– Configuration Base Address (CBAR) register (Port FFFCh) to set the MMCR's base
address (accessible only by the CPU)
System Address Mapping
86 CPU, the PCI bus, and the GP bus DMA controller.
x
86 CPU and the PCI bus each implement separate memory and I/O address
x
GP
SDRAM ROM Bus
86 CPU and PCI bus definition support separate memory and I/O address spaces
x
Élan™SC520 Microcontroller User's Manual
Integrated Integrated
PCI PC/AT Non-PC/AT
Bus Peripherals Peripherals
Memory-
Mapped CBAR
Registers Register
4-3