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3.2
BUS OPERATION
The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address
and data (AD) bus. The address is present on the AD bus only during the t
The Am186ES and Am188ES microcontrollers continue to provide the multiplexed AD bus
and, in addition, provide a nonmultiplexed address (A) bus. The A bus provides an address
to the system for the complete bus cycle (t
For systems where power consumption is a concern, it is possible to disable the address
from being driven on the AD bus on the Am186ES microcontroller and on the AD and AO
buses on the Am188ES microcontroller during the normal address portion of the bus cycle
for accesses to UCS and/or LCS address spaces. In this mode, the affected bus is placed
in a high impedance state during the address portion of the bus cycle. This feature is enabled
through the DA bits in the UMCS and LMCS registers. When address disable is in effect,
the number of signals that assert on the bus during all normal bus cycles to the associated
address space is reduced, thus decreasing power consumption, reducing processor
switching noise, and preventing bus contention with memory devices and peripherals when
operating at high clock rates. On the Am188ES microcontroller, the address is driven on
A015–A08 during the data portion of the bus cycle, regardless of the setting of the DA bits.
If the ADEN pin is pulled Low during processor reset, the value of the DA bits in the UMCS
and LMCS registers is ignored and the address is driven on the AD bus for all accesses,
thus preserving the industry-standard 80C186 and 80C188 microcontrollers' multiplexed
address bus and providing support for existing emulation tools.
Figure 3-1 shows the affected signals during a normal read or write operation for an
Am186ES microcontroller. The address and data will be multiplexed onto the AD bus.
Figure 3-2 shows an Am186ES microcontroller bus cycle when address bus disable is in
effect. This results in the AD bus operating in a nonmultiplexed data-only mode. The A bus
will have the address during a read or write operation.
Figure 3-3 shows the affected signals during a normal read or write operation for an
Am188ES microcontroller. The multiplexed address/data mode is compatible with the
80C188 microcontrollers and might be used to take advantage of existing logic or
peripherals.
Figure 3-4 shows an Am188ES microcontroller bus cycle when address bus disable is in
effect. The address and data are not multiplexed. The AD7–AD0 signals will have only data
on the bus, while the AO bus will have the address during a read or write operation.
3-20
–t
).
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4
System Overview
clock phase.
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