NAD C715 Service Manual page 41

Signal Name Shared Signal
GPIO_A[0] SDO0 / FGPIO[0]
GPIO_B[29:28] USBH_DN, USBH_DP
GPIO_B[27:26] USB_DN, USB_DP
GPIO_B[25] DAI
GPIO_B[24] / BM[2] DAO
GPIO_B[23] MCLK
GPIO_B[22] / BM[1] LRCK
GPIO_B[21] / BM[0] BCLK
GPIO_B[9] UT_RX
GPIO_B[8] UT_TX / SD_nCS
GPIO_B[7] ND_nWE
GPIO_B[5:2] nCS[3:0]
GPIO_B[1] SD_nCS / SD_nCLK
GPIO_B[0] SD_CKE
GPIO_D[21:18] FGPIO[13:10] / CISD[7:4]
GPIO_D[17] FGPIO[9] / SCL / CISHS
GPIO_D[16] FGPIO[8] / SDA / CISVS
GPIO_D[15] CISCLK
ADIN_0 -
ADIN_2 -
ADIN_4 -
XIN -
XOUT -
XFILT -
XTIN -
XTOUT -
MODE1 -
PKG1 -
nRESET -
TDI -
TMS -
TCK -
TDO -
nTRST -
VDDIO -
Pin # Type Description – TCC760
GPIO_A[0] / General purpose serial I/O 0 Serial Data Output
104 I/O
FGPIO[0]
54:53 I/O GPIO_B[29:28] / USBH_DN, USBH_DP
52:51 I/O GPIO_B[27:26] / USB_DN, USB_DP
68 GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals.
67 The status of BM[2:0] is latched at the rising edge of nRESET and
66 I/O used to determine the system boot mode. Refer to sections
63 "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for
62 detailed description on BM[2:0].
61 I/O GPIO_B[9 ] / UART RX Signal
60 I/O GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select
57 I/O GPIO_B[7] / Write Enable for NAND Flash
50:47 I/O GPIO_B[5:2] / External Chip Select 3 ~ 0
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
46 I/O
SDRAM.
56 I/O GPIO_B[0] / SDRAM clock control
GPIO_D[21:18] / Fast GPIO bits 13 ~10 / Camera Interface Data
96:93 I/O
Inputs 3 ~ 0. Internal pull-up resistors are enabled at reset.
92 I/O GPIO_D[17] / Fast GPIO bit 9 / I2C SCL / Camera Interface Hsync.
91 I/O GPIO_D[16] / Fast GPIO bit 8 / I2C SDA / Camera Interface Vsync.
90 I/O GPIO_D[15] / Camera Interface Clock
82 AI General purpose multi-channel ADC input 0
83 AI General purpose multi-channel ADC input 2
84 AI General purpose multi-channel ADC input 4
74 I Main Crystal Oscillator Input for PLL. 12MHz Crystal
must be used if USB Boot Mode is required. Input
voltage must not exceed VDD_OSC (1.95V max).
75 O Main Crystal Oscillator Output for PLL
78 AO PLL filter output
69 I Sub Crystal Oscillator Input. 32.768kHz is recommended.
Input voltage must not exceed VDD_OSC (1.95V max).
70 O Sub Crystal Oscillator Output
98 I Mode Setting Input 1. Pull-down for normal operation.
89 I Package ID1, Pull-up for normal operation.
72 I System Reset. Active low.
99 I JTAG serial data input for ARM940T
100 I JTAG test mode select for ARM940T
101 I JTAG test clock for ARM940T
102 I/O JTAG serial data output for ARM940T. External pull-up resistor is
required to prevent floating during normal operation.
103 I JTAG reset signal for ARM940T. Active low.
112 PWR Digital Power for I/O (1.8V ~ 3.3V)
76
33
16
2-30
ADC Input Pins
Clock Pins
Mode Control Pins
JTAG Interface Pins
Power Pins