NAD C715 Service Manual page 40

Signal Name Shared Signal
XD[3:0]
NCS[3:0] ND_nOE[3:0] / GPIO_B[5:2]
ND_nWE GPIO_B[7]
nWE
nOE
READY
USB_DP GPIO_B[26]
USB_DN GPIO_B[27]
USBH_DP GPIO_B[28]
USBH_DN GPIO_B[29]
UT_TX GPIO_B[8] / SD_nCS
UT_RX GPIO_B[9] / IDE_nCS1
BCLK GPIO_B[21] / BM[0]
LRCK GPIO_B[22] / BM[1]
MCLK GPIO_B[23]
DAO GPIO_B[24] / BM[2]
DAI GPIO_B[25]
CBCLK GPIO_A[1]
CLRCK GPIO_A[2]
CDAI GPIO_A[3]
EXINT[3] GPIO_A[15]
EXINT[2:0] GPIO_A[14:12] / FGPIO[14:12] 123:121
CISHS GPIO_D[17]
CISVS GPIO_D[16]
CISCLK GPIO_D[15]
CISD[7:4] GPIO_D[21:18]
CISD[3:0] GPIO_A[3:0]
GPIO_A[15] EXINT[3]
GPIO_A[14:12] EXINT[2:0] / FGPIO[14:12]
GPIO_A[11] SDI2 / FGPIO[11] / SCL
GPIO_A[10] FRM2 / FGPIO[10] / SDA
GPIO_A[9] / BW[1] SCK2 / FGPIO[9] / SCL
GPIO_A[8] / BW[0] SDO2 / FGPIO[8] / SDA
SDI1 / FGPIO[7]
FRM1 / FGPIO[6]
GPIO_A[7:4]
SCK1 / FGPIO[5]
SDO1 / FGPIO[4]
SDI0 / CDAI / FGPIO[3]
GPIO_A[3:1] FRM0 / CLRCK / FGPIO[2]
SCK0 / CBCLK / FGPIO[1]
Pin # Type Description – TCC760
128:125
External Bus Chip Select [3:0] / NAND Flash Output Enable
50:47 I/O
[3:0] / GPIO_B[5:2]
57 I/O NAND flash WE. Active low. / GPIO_B[7]
58 I/O Static Memory Write Enable signal. Active low.
59 I/O Static Memory Output Enable signal. Active low.
73 I Ready information from external device.
51 I/O USB Function D+ signal / GPIO_B[26]
52 I/O USB Function D- signal / GPIO_B[27]
53 I/O USB Host D+ signal / GPIO_B[28]
54 I/O USB Host D- signal / GPIO_B[29]
UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip
60 I/O
Select
61 I/O UART or IrDA RX data / GPIO_B[9] / IDE Chip Select 1
62 I/O I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0
63 I/O I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1
66 I/O I2S System Clock / GPIO_B[23]
I2S Digital Audio data Output / GPIO_B[24] / Boot Mode
67 I/O
Bit 2
68 I/O I2S Digital Audio data Input / GPIO_B[25]
105 I/O CD Data Bit Clock Input / GPIO_A[1]
106 I/O CD Data Word Clock Input / GPIO_A[2]
107 I/O CD Data Input / GPIO_A[3]
124 I/O External Interrupt Request [3] / GPIO_A[15]
I/O External Interrupt Request [2:0] / GPIO_A[14:12] / FGPIO[14:12]
92 I/O Horizontal Sync. Input / GPIO_D[17]
91 I/O Vertical Sync. Input / GPIO_D[16]
90 I/O Clock Input / GPIO_D[15]
96:93
I/O Data Input[7:0] / GPIO_D[21:18], GPIO_A[3:0]
107:104
124 I/O GPIO_A[15] / External Interrupt 3
123:121 I/O GPIO_A[15:12] / External Interrupt 3 ~ 0 / Fast GPIO bits 14 ~ 12
GPIO_A[11:8] / Bus Width bits 1 ~ 0 / General Purpose Serial I/O 2
Fast GPIO bits 11 ~ 8 / I2C signals.
118:115 I/O The status of BW[1:0] is latched at the rising edge of nRESET and
used to determine external bus width. Refer to section "MEMORY
CONTROLLER" for BW[1:0] description.
114
113
I/O GPIO_A[7:4] / General Purpose Serial I/O 1 / Fast GPIO bits 7 ~ 4
111
108
GPIO_A[3:1] / General Purpose Serial I/O 0 / CD Interface Signals /
107:105 I/O
Fast GPIO bits 3 ~ 1
2-29
USB/UART/IrDA Interface Pins
Audio Interface Pins
CD DSP Interface Pins
External Interrupt Pins
Camera Interface Pins
General Purpose I/O Pins