Dds Mode - Fluke 281 User Manual

40 ms/s arbitrary waveform generators
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Users Manual

DDS Mode

In DDS mode all waveforms are stored in RAM as 4096 points. The frequency of the
output waveform is determined by the rate at which the RAM addresses are changed. The
address changes are generated as follows:
The RAM contains the amplitude values of all the individual points of one cycle (360 º)
of the waveform; each sequential address change corresponds to a phase increment of the
waveform of 360/4096 degrees. Instead of using a counter to generate sequential RAM
addresses, a phase accumulator is used to increment the phase.
On each clock cycle the phase increment, which has been loaded into the phase increment
register by the CPU, is added to the current result in the phase accumulator; the 12 most
significant bits of the phase accumulator drive the lower 12 RAM address lines, the upper
4 RAM address lines being held low. The output waveform frequency is now determined
by the size of the phase increment at each clock. If each increment is the same size then
the output frequency is constant; if it changes, the output frequency changes as in sweep
mode.
The generator uses a 38 bit accumulator and a clock frequency which is 2
(approximately 27·4878 MHz); this yields a frequency resolution of 0·1 mHz.
Only the 12 most significant bits of the phase accumulator are used to address the RAM.
At a waveform frequency equal to the clock frequency divided by 4096, approximately
6·7 kHz, the natural frequency, the RAM address increments at every clock. At all
frequencies below this (i.e. at smaller phase increments) one or more addresses are output
for more than one clock period because the phase increment is not big enough to step the
address at every clock. Similarly at frequencies above the natural frequency the larger
phase increment causes some addresses to be skipped, giving the effect of the stored
waveform being sampled; different points will be sampled on successive cycles of the
waveform.
4-6
Figure 4-2. Clock Synthesis Mode
Figure 4-3. Direct Digital Synthesis Mode
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