Biostar M6VLQ Grand Manual page 52

M6VLQ Grand BIOS Setup
AGP Master 1 WS Write
The Choices: Enabled, Disabled (default).
AGP Master 1 WS Read
When Enabled, read to the AGP (Accelerated Graphics Port) are executed with
one wait states.
The Choices: Disabled (default), Enabled.
CPU & PCI Bus Control
If you highlight the literal "Press Enter" next to the "CPU & PCI Bus Control" label and
then press the enter key, it will take you a submenu with the following options:
CPU to PCI Write Buffer
When enabled, up to four Dwords of data. Can be written to the PCI bus without
interrupting the CPU. When disabled, a write buffer is not used and the CPU read
cycle will not be completed until the PCI bus signals that it is ready to receive the
data.
The Choices: Enabled (default), Disabled.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero-wait states.
The Choices: Enabled (default), Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification.
The Choices: Disabled, Enabled (default).
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved it cannot be cached. The user information of peripherals that need to use this area
of system memory usually2 discussed their memory requirements.
The Choices: Disabled (default), Enabled.
System BIOS Cacheable
Selecting the "Enabled" option allows caching of the system BIOS ROM at
F0000h-FFFFFh which can improve system performance.
writing to this area of memory will cause conflicts and result in system errors.
The Choices: Enabled, Disabled (default).
Video RAM Cacheable
Enabling this option allows caching of the video RAM, resulting a better system
performance. However, if any program writes to this memory area, a system error may
result.
The Choices: Disabled (default), Enabled.
However, any programs
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