Mitsubishi MELSEC-q Programming Manual page 8

Melsec q series; melsec l series
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5.5.17 Increment ................................................................................................. INC_M .......................... 5-21
5.5.18 Decrement ............................................................................................... DEC_M......................... 5-21
5.5.19 32-bit BIN increment ............................................................................... DINC_M........................ 5-22
5.5.20 32-bit BIN decrement .............................................................................. DDEC_M ...................... 5-22
5.6 Data Conversion ...................................................................................................................................... 5-23
5.6.2 32-bit BIN
BCD conversion .................................................................. DBCD_M ...................... 5-23
5.6.15 Complement of 2 of 16-bit BIN ............................................................... NEG_M......................... 5-30
5.6.16 Complement of 2 of 32-bit BIN ............................................................... DNEG_M...................... 5-30
5.6.17 Complement of 2 of floating-point ........................................................... ENEG_M ...................... 5-31
5.7 Data Transfer ........................................................................................................................................... 5-33
5.7.1 16-bit data NOT transfer ........................................................................... CML_M......................... 5-33
5.7.2 32-bit data NOT transfer ........................................................................... DCML_M ...................... 5-33
5.7.3 Block transfer ............................................................................................. BMOV_M...................... 5-34
5.7.4 Same data block transfer .......................................................................... FMOV_M...................... 5-34
5.7.5 16-bit data exchange ................................................................................. XCH_M......................... 5-35
5.7.6 32-bit data exchange ................................................................................. DXCH_M ...................... 5-35
5.7.7 Block data exchange ................................................................................. BXCH_M ...................... 5-36
5.7.8 First/last byte exchange ............................................................................ SWAP_MD ................... 5-36
5.8 Program Execution Control...................................................................................................................... 5-37
5.8.1 Interrupt disable ......................................................................................... DI_M ............................. 5-37
5.8.2 Interrupt enable ......................................................................................... EI_M ............................. 5-37
5.9 I/O Refresh ............................................................................................................................................... 5-38
5.9.1 I/O refresh .................................................................................................. RFS_M ......................... 5-38
5.10 Logical Operation Commands............................................................................................................... 5-39
5.10.1 Logical product (2 devices) ..................................................................... WAND_M ..................... 5-39
5.10.2 Logical product (3 devices) ..................................................................... WAND_3_M ................. 5-39
5.10.3 32-bit data logical product (2 devices) .................................................... DAND_M ...................... 5-40
5.10.4 32-bit data logical product (3 devices) .................................................... DAND_3_M .................. 5-40
5.10.5 Block data logical product ....................................................................... BKAND_M.................... 5-41
5.10.6 Logical sum (2 devices) .......................................................................... WOR_M........................ 5-41
5.10.7 Logical sum (3 devices) .......................................................................... WOR_3_M ................... 5-42
5.10.8 32-bit data logical sum (2 devices) ......................................................... DOR_M ........................ 5-42
5.10.9 32-bit data logical sum (3 devices) ......................................................... DOR_3_M .................... 5-43
A - 6
A - 6

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