Mitsubishi MELSEC-Q/L Programming Manual

page of 850

/ 850
Contents
Table of Contents
Bookmarks

Table of Contents

Quick Links

Download this manual

Table of Contents

Summary of Contents for Mitsubishi MELSEC-Q/L

Page 3: Safety Precautions
SAFETY PRECAUTIONS (Always read these cautions before using the product) Before using this product, please read this manual and the related manuals introduced in this manual, and pay full attention to safety to handle the product correctly. Please store this manual in a safe place and make it accessible when required. Always forward a copy of the manual to the end user.
Page 4: Conditions Of Use For The Product
CONDITIONS OF USE FOR THE PRODUCT (1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions; i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any major or serious accident; and ii) where the backup and fail-safe function are systematically or automatically provided outside of the PRODUCT for the case of any problem, fault or failure occurring in the PRODUCT.
Page 5: Revisions
REVISIONS *The manual number is given on the bottom left of the back cover. Print Date *Manual Number Revision Dec., 2008 SH (NA)-080809ENG-A First edition Mar., 2009 SH (NA)-080809ENG-B Partial corrections Section 3.3, 3.8, 5.1.3, 6.1.7, 6.2.14, 7.3.3, 7.11.18, 7.11.19, 7.12.1.5,12.7, 7.12.11, 7.12.25, 7.12.26, 7.13.4, 7.13.5, 7.15.7, 7.15.8 Jul., 2009 SH (NA)-080809ENG-C Revision because of function support by the Universal model QCPU having a...
Page 6 This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.
Page 7: Introduction
INTRODUCTION This document is the MELSEC-Q/L Programming Manual (Common Instructions). It describes the common instructions required for programming of the QCPU and LCPU. • "Common instructions" are all instructions except for dedicated instructions for such intelligent function modules as QJ71C24N and QJ71E71-100; PID control instructions; SFC instructions; ST instructions; instructions for socket communication features;...
Page 8: Table Of Contents
CONTENTS CONTENTS SAFETY PRECAUTIONS ............. 1 CONDITIONS OF USE FOR THE PRODUCT .
Page 9 2.5.16 Expansion clock instructions ..........75 2.5.17 Program control instructions .
Page 10 5.1.3 LDPI, LDFI Pulse NOT operation start ......128 ANDPI, ANDFI Pulse NOT series connection ......128 ORPI, ORFI Pulse NOT parallel connection .
Page 11 6.1.3 E=, E<>, E>, E<=, E<, Floating-point data comparisons (Single precision) ..175 E>= 6.1.4 ED=, ED<>, ED>, ED<=, Floating-point data comparisons (Double precision) ..177 ED<, ED>= 6.1.5 $=, $<>, $>, $<=, $<, Character string data comparisons .
Page 12 6.3.5 INT, INTP Conversion from floating-point data to BIN 16-bit data (Single precision) ........238 DINT, DINTP Conversion from floating-point data to BIN 32-bit data (Single precision) .
Page 13 I/O Refresh Instructions ............285 6.7.1 RFS, RFSP I/O refresh .
Page 14 Bit processing instructions ........... . 349 7.4.1 BSET, BSETP Bit set for word devices .
Page 15 7.7.2 FIFR, FIFRP Reading oldest data from tables ......419 7.7.3 FPOP, FPOPP Reading newest data from data tables ....421 7.7.4 FDEL, FDELP Deletion of data from data tables .
Page 16 7.11.21 EREXP, EREXPP From BCD format data to floating-point data ....498 7.12 Special function instructions........... 500 7.12.1 SIN, SINP SIN operation on floating-point data (Single precision) .
Page 17 7.12.28 BSQR, BSQRP BCD 4-digit square roots ......540 BDSQR, BDSQRP BCD 8-digit square roots ......540 7.12.29 BSIN, BSINP BCD type SIN operation .
Page 18 7.18 Other instructions............605 7.18.1 WDT, WDTP Watchdog timer reset .
Page 19 CHAPTER 11 REDUNDANT SYSTEM INSTRUCTIONS (For REDUNDANT CPU) 703 11.1 SP.CONTSW System Switching ........703 APPENDICES Appendix 1 OPERATION PROCESSING TIME .
Page 20: Manuals
MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following list. The numbers in the "CPU module"...
Page 21 Basic manual, :Other CPU module manuals Manual name CPU module Description < Manual number (model code) > Programming Manual MELSEC-Q /L Programming Manual How to use sequence instructions, basic (Common Instructions) instructions, and application instructions < SH-080809ENG (13JW10) > System configuration, performance specifications, MELSEC-Q /L/QnA Programming Manual (SFC) functions, programming, debugging, and error <...
Page 22: Chapter 1 General Description
(1) Basic model QCPU Qn(H)/QnPH/ Describes the functions QnPRHCPU and devices of the CPU User's Manual module, and programming. (Function Explanation, Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L Programming QnA Programming QnA Programming Programming Programming Manual Manual (Common...
Page 23 (2) High Performance model QCPU Qn(H)/QnPH/ QnPRHCPU Describes the functions User's Manual and devices of the CPU (Function Explanation, module, and programming. Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L Programming QnA Programming QnA Programming Programming Programming Manual (Common...
Page 24 (4) Redundant CPU Qn(H)/QnPH/ Describes the functions and devices QnPRHCPU of the CPU module, and programming. User's Manual (Function Explanation, Program Fundamentals) This manual MELSEC-Q/L QnPHCPU/ MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L Programming Manual Programming Manual Programming Manual Programming Manual QnPRHCPU (Common Instructions)
Page 25: Abbreviations And Generic Names
Generic term/Abbreviation Description of Generic Name/Abbreviation Series Q series Abbreviation for Mitsubishi MELSEC-Q series programmable controller L series Abbreviation for Mitsubishi MELSEC-L series programmable controller CPU module type Generic term for Basic model QCPU, High Performance model QCPU, Process CPU,...
Page 26 (Continued) Generic Name/Abbreviation Description of Generic Name/Abbreviation Generic term for Q32SB, Q33SB and Q35SB slim type main base units on which Basic model QCPU (except Q00JCPU), High Performance model QCPU, slim type power supply module, Q series I/O Q3 SB module, and intelligent function module can be mounted.
Page 27: Chapter 2 Instruction Tables
CHAPTER 2 INSTRUCTION TABLES Types of Instructions The major types of CPU module instructions consist of sequence instructions, basic instructions, application instructions, data link instructions, QCPU instructions and redundant system instructions. These types of instructions are listed in the following Table.
Page 28 Reference Types of Instruction Meaning Chapter Reading/writing of the values of year, month, day, hour, minute, second, and day of the week; addition/subtraction of the values of hour, minute, and Clock instruction second; conversion of the values of hour, minute, and second into second; comparison between the values of year, month, and day;...
Page 29: How To Read Instruction Tables
How to Read Instruction Tables The instruction tables found from Page 29, Section 2.3 to Page 51, Section 2.5 have been made according to the following format: Description 1)....Classifies instructions according to their application. 2)....Indicates the instruction symbol added to the instruction in a program. Instruction code is built around the 16-bit instruction.
Page 30 3)....Shows symbol diagram on the ladder. S1 S2 Indicates destination. Indicates destination. Indicates source. Indicates source. Indicates instruction symbol. Indicates instruction symbol. Fig. 2.1 Symbol Diagram on the Ladder Destination....Indicates where data will be sent after operation. Source..... Stores data prior to operation. 4)....Indicates the type of processing that is performed by individual instructions.
Page 31: Sequence Instructions
Sequence Instructions 2.3.1 Contact instructions Execution Category Symbol Processing Details Condition • Starts logic operation (Starts a contact logic operation) • Starts logical NOT operation (Starts b contact logic operation) • Logical product (a contact series connection) Page • Logical product NOT (b contact series connection) •...
Page 32: Association Instructions
The number of steps may vary depending on the device and type of CPU module being used. Device Number of Steps Internal device, file register (R0 to R32767) Direct access input (DX) Devices other than above The number of steps may vary depending on the device being used. Device Number of Steps Internal device, file register (R0 to R32767)
Page 33: Output Instructions
2.3.3 Output instructions Execution Category Symbol Processing Details Condition Page Page • Device output Page Page Page • Sets device Page Page Output • Resets device Page • Generates 1 cycle program pulse at leading edge of input signal. Page •...
Page 34: Master Control Instructions
2.3.5 Master control instructions Execution Category Symbol Processing Details Condition • Starts master control Master Page control • Resets master control 2.3.6 Termination instructions Execution Category Symbol Processing Details Condition Page FEND • Termination of main program FEND Termination Page •...
Page 35: Basic Instructions
Basic instructions 2.4.1 Comparison operation instructions Execution Category Symbol Processing Details Condition S1 S2 AND= • Conductive status when (S1) (S2) S1 S2 • Non-conductive status when (S1) (S2) S1 S2 LD<> S1 S2 AND<> • Conductive status when (S1) (S2) S1 S2 •...
Page 36 Execution Category Symbol Processing Details Condition LDD= S1 S2 • Conductive status when ANDD= (S1+1, S1) (S2+1, S2) S1 S2 • Non-Conductive status when ORD= (S1+1, S1) (S2+1, S2) S1 S2 LDD<> S1 S2 • Conductive status when ANDD<> (S1+1, S1) (S2+1, S2) S1 S2 •...
Page 37 Execution Category Symbol Processing Details Condition LDE= S1 S2 • Conductive status when ANDE= (S1+1, S1) (S2+1, S2) S1 S2 • Non-Conductive status when ORE= (S1+1, S1) (S2+1, S2) S1 S2 LDE<> S1 S2 • Conductive status when ANDE<> (S1+1, S1) (S2+1, S2) S1 S2 •...
Page 38 Execution Category Symbol Processing Details Condition • Conductive status when LDED= S1 S2 (S1+3, S1+2, S1+1, S1) ANDED= S1 S2 (S2+3, S2+2, S2+1, S2) • Non-Conductive status when ORED= (S1+3, S1+2, S1+1, S1) S1 S2 (S2+3, S2+2, S2+1, S2) • Conductive status when LDED<>...
Page 39 Execution Category Symbol Processing Details Condition • Compares character string S1 and character LD$= S1 S2 string S2 one character at a time. *2 • Conductive status when (character string S1) AND$= S1 S2 (character string S2) • Non-Conductive status when (character string OR$= S1 S2 (character string S2)
Page 40 Execution Category Symbol Processing Details Condition BKCMP= BKCMP S1 S2 D BKCMP<> BKCMP S1 S2 D BKCMP> BKCMP S1 S2 D BKCMP<= BKCMP S1 S2 D • This instruction compares BIN 16-bit data BKCMP< BKCMP S1 S2 D stored in n-point devices starting from the BIN 16-bit device specified by S1 with BIN 16-bit BKCMP>=...
Page 41: Arithmetic Operation Instructions
2.4.2 Arithmetic operation instructions Execution Category Symbol Processing Details Condition Page • (D)+(S) (D) S1 S2 D Page • (S1)+(S2) (D) BIN 16-bit S1 S2 D addition and subtraction Page operations • (D)-(S) (D) S1 S2 D Page • (S1)-(S2) (D) S1 S2 D Page •...
Page 42 The number of steps may vary depending on the device and type of CPU module being used. Number of Component Device Steps • Word device: Internal device (except for file register ZR) • Bit device: Devices whose device Nos. are multiples of 16, whose digit High Performance model QCPU Note 1) designation is K8, and which use no indexing.
Page 43 Execution Category Symbol Processing Details Condition Page • (D)+(S) (D) S1 S2 D Page • (S1)+(S2) (D) BCD 4-digit S1 S2 D addition and subtraction Page operations • (D)-(S) (D) S1 S2 D Page • (S1)-(S2) (D) S1 S2 D Page •...
Page 44 Execution Category Symbol Processing Details Condition Page • (D+1, D)+(S+1, S) (D+1, D) Floating decimal S1 S2 D Page • (S1+1, S1)+(S2+1, S2) (D+1, D) point data S1 S2 D addition and subtraction Page operations • (D+1, D)-(S+1, S) (D+1, D) (Single precision) S1 S2 D...
Page 45 Execution Category Symbol Processing Details Condition • This instruction adds BIN 16-bit data stored in S1 S2 n-point devices starting from the device specified by (S1) to the n-point data stored in BIN 16-bit the devices starting from the device specified BK+P BK+P S1 S2...
Page 46: Data Conversion Instructions
The number of steps may vary depending on the device and type of CPU module being used. Number of Component Device Steps • Word device: Internal device (except for file register ZR) • Bit device: Devices whose device Nos. are multiples of 16, whose digit High Performance model QCPU Note 1) designation is K8, and which use no indexing.
Page 47 Execution Category Symbol Processing Details Condition Floating point Conversion to BIN (S+1, S) INTP INTP Real number (-32768 to 32767) Page conversions DINT Conversion to BIN DINT (Single (S+1, S) (D+1, D) precision) Real number (-2147483648 to DINTP DINTP 2147483647) INTD Conversion to BIN Floating point...
Page 48 Execution Category Symbol Processing Details Condition BIN data NEGP NEGP Page DNEG DNEG (D+1, D) (D+1, D) BIN data DNEGP DNEGP Complement to 2 ENEG ENEG Page (D+1, D) (D+1, D) Real number data ENEGP ENEGP EDNEG EDNEG Page (D+3, D+2, D+1, D) (D+3, D+2, D+1, D) Real number data EDNEGP...
Page 49: Data Transfer Instructions
2.4.4 Data transfer instructions Execution Category Symbol Processing Details Condition 16-bit data ( D ) transfer MOVP MOVP Page DMOV DMOV 32-bit data (S+1,S) (D+1,D) transfer DMOVP DMOVP Floating EMOV EMOV decimal point Page (S+1, S) (D+1, D) data transfer Real number data (Single EMOVP...
Page 50 Execution Category Symbol Processing Details Condition BXCH BXCH Block data Page exchange BXCHP BXCHP b15 to b8 b7 SWAP SWAP Exchange of 8 bits 8 bits Page upper and lower bytes SWAPP b15 to b8 b7 SWAPP 8 bits 8 bits The number of steps may vary depending on the device and type of CPU module being used.
Page 51: Program Branch Instructions
2.4.5 Program branch instructions Execution Category Symbol Processing Details Condition • Jumps to Pn when input conditions are met. Page • Jumps to Pn from the scan after the meeting of input condition. Jump • Jumps unconditionally to Pn. • Jumps to END instruction when input Page GOEND GOEND...
Page 52: Other Convenient Instructions
2.4.8 Other convenient instructions Execution Category Symbol Processing Details Condition (S)+0 Page Down UDCNT1 (S)+1 UDCNT1 Present Cn value 1 2 3 4 6 7 6 5 3 2 1 0 -1 -2 -3 -2 -1 0 Up/Down Cn contact counter (S)+0 Page...
Page 53: Application Instructions
Application Instructions 2.5.1 Logical operation instructions Execution Category Symbol Processing Details Condition WAND WAND Page WANDP WANDP WAND WAND S1 S2 D Page (S1) (S2) WANDP WANDP S1 S2 D DAND DAND Page Logical (S+1,S) (D+1,D) (D+1,D) product DANDP DANDP DAND DAND S1 S2 D...
Page 54 Execution Category Symbol Processing Details Condition DXOR DXOR S1 S2 D Page (S1+1,S1) (S2+1,S2) (D+1,D) DXORP DXORP S1 S2 D Exclusive BKXOR (S1) (S2) BKXOR S1 S2 D Page BKXORP BKXORP S1 S2 D WXNR WXNR Page WXNRP WXNRP WXNR WXNR S1 S2 D Page...
Page 55: Rotation Instructions
The number of steps may vary depending on the device and type of CPU module being used. Number of Component Device Steps • Word device: Internal device (except for file register ZR) • Bit device: Devices whose device Nos. are multiples of 16, whose digit High Performance model QCPU Note 1) designation is K8, and which use no indexing.
Page 56: Shift Instructions
Execution Category Symbol Processing Details Condition (D+1) DROL DROL SM700 b15 to DROLP DROLP Left Page Carry flag Left rotation by n bits rotation (D+1) DRCL DRCL SM700 b15 to DRCLP DRCLP Carry flag Left rotation by n bits 2.5.3 Shift instructions Execution Category...
Page 57 Execution Category Symbol Processing Details Condition SFTBR SFTBR SFTBR D n1 n2 D n1 n2 Carry flag SFTBRP SFTRP D n1 n2 SM700 n-bit shift of Page n-bit data SFTBL SFTBL D n1 n2 Carry flag SFTBLP SFTBLP D n1 n2 SM700 DSFR DSFR...
Page 58: Bit Processing Instructions
2.5.4 Bit processing instructions Execution Category Symbol Processing Details Condition BSET BSET BSETP BSETP Page set/reset BRST BRST BRSTP BRSTP (S1) TEST TEST S1 S2 D TESTP TESTP S1 S2 D Page Bit designated by (S2) Bit tests (S1) DTEST DTEST S1 S2 D DTESTP...
Page 59 Execution Category Symbol Processing Details Condition SUMP SUMP Page (D): Number of 1s Bit checks DSUM (S + 1) DSUM DSUMP DSUMP (D): Number of 1s DECO Decode from 8 to 256 DECO Page Decode Decode DECOP bits DECOP ENCO Decode from 256 to 8 ENCO Page...
Page 60 Execution Category Symbol Processing Details Condition • Searches the data of n points from the device designated by (S) in 16-bit units, Page and stores the maximum value at the MAXP MAXP device designated by (D). • Searches the data of n points from the device designated by (S) in 16-bit units, Page and stores the minimum value at the...
Page 61: Structure Creation Instructions
2.5.6 Structure creation instructions Execution Category Symbol Processing Details Condition • Executes n times between the Page NEXT NEXT NEXT Number of repeats • Forcibly ends the execution of the BREAK BREAK Page NEXT cycle and jumps BREAKP BREAKP pointer Pn. CALL CALL •...
Page 62 Execution Category Symbol Processing Details Condition EFCALL EFCALL • Performs non-execution processing of EFCALL Pn S1toSn subroutine program Pn if input Page :File name conditions have not been met. (S1 to Sn are arguments sent to subroutine EFCALLP program. N EFCALLP Subroutine EFCALLP...
Page 63: Data Table Operation Instructions
2.5.7 Data table operation instructions Execution Category Symbol Processing Details Condition Pointer Pointer + 1 FIFW FIFW Page FIFWP Device at FIFWP pointer + 1 (S) Pointer Pointer - 1 FIFR FIFR Page FIFRP FIFRP (S) Pointer Pointer - 1 FPOP FPOP Page...
Page 64: Buffer Memory Access Instructions
2.5.8 Buffer memory access instructions Execution Category Symbol Processing Details Condition FROM FROM n1 n2 D • Reads data in 16-bit units from an intelligent function module. FROMP FROMP n1 n2 D Page Data read DFRO DFRO n1 n2 D •...
Page 65: Debugging And Failure Diagnosis Instructions
2.5.10 Debugging and failure diagnosis instructions Execution Category Symbol Processing Details Condition • The CHK instruction is executed when CHKST is executable. CHKST • Jumps to the step following the CHK CHKST instruction when CHKST is in a Page non-executable status. •...
Page 66 Execution Category Symbol Processing Details Condition • Converts 1-word BCD value designated by BCDDA BCDDA (S) to a 4-digit, decimal ASCII value, and stores it at a word device following the word BCDDAP BCDDAP device number designated by (D). Page Decimal •...
Page 67 Execution Category Symbol Processing Details Condition • Converts a 1-word BIN value designated by (S2) to a decimal character string with the S1 S2 D total number of digits and the number of decimal fraction digits designated by (S1) STRP and stores them at a device designated by STRP S1 S2 D...
Page 68 Execution Category Symbol Processing Details Condition • Stores n characters from the end of a RIGHT RIGHT character string designated by (S) at the RIGHTP device designated by (D). RIGHTP Page • Stores n characters from the beginning of a LEFT LEFT character string designated by (S) at the...
Page 69: Special Function Instructions
2.5.12 Special function instructions Execution Category Symbol Processing Details Condition Page Sin (S+1,S) (D+1,D) SINP SINP Page (D+1,D) Cos (S+1,S) COSP COSP Page Trigonometric Tan(S+1,S) (D+1,D) functions TANP TANP (Floating- ASIN point single- ASIN Page (S+1,S) (D+1,D) precision) ASINP ASINP ACOS ACOS Page...
Page 70 Execution Category Symbol Processing Details Condition Page (S+1, S) (D+1, D) Conversion from angles to radians RADP RADP RADD RADD Page (D+3, D+2, D+1, D) (S+3, S+2, S+1, S) Angles Conversion from angle to radian RADDP RADDP Radians Page (D+1, D) (S+1, S) conversion Conversion from radians to angles...
Page 71 Execution Category Symbol Processing Details Condition Random • Generates a random number (from 0 to less number than 32767) and stores it at the device RNDP generation designated by (D). RNDP Page Random SRND • Updates random number series according to SRND number the 16-bit BIN data stored in the device...
Page 72: Data Control Instructions
2.5.13 Data control instructions Execution Category Symbol Processing Details Condition • When (S3) (S1) LIMIT ...Stores value of (S1) at (D) LIMIT S1 S2 • When (S1) (S3) (S2) ...Stores value of (S3) at (D) • When (S2) (S3) LIMITP LIMITP S1 S2 Upper and...
Page 73 Execution Category Symbol Processing Details Condition • Executes scaling for the scaling conversion data (16-bit data units) specified by (S2) with S1 S2 D the input value specified by (S1), and then stores the result into the device specified by (D).
Page 74: Switching Instructions
2.5.14 Switching instructions Execution Category Symbol Processing Details Condition Block RSET RSET • Converts extension file register block number Page number to number designated by (S). RSETP switching RSETP QDRSET QDRSET File name Page • Sets file names used as file registers. QDRSETP QDRSETP File name File set...
Page 75 Execution Category Symbol Processing Details Condition SECOND SECOND S D Page Hour Sec. (Lower 16 bits) Sec. (Upper 16 bits) Minute SECONDP SECONDP S D Clock data Sec. translation HOUR HOUR Page Sec. (Lower 16 bits) Hour Sec. (Upper 16 bits) Mitnute HOURP HOURP...
Page 76 Execution Category Symbol Processing Details Condition LDTM= S1 S2 n Hour Hour ANDTM= S1 S2 Comparison Minute Minute operation result Second Second ORTM= S1 S2 LDTM<> S1 S2 n Hour Hour ANDTM<> S1 S2 n Comparison Minute Minute operation result Second Second ORTM<>...
Page 77: Expansion Clock Instructions
2.5.16 Expansion clock instructions Execution Category Symbol Processing Details Condition (Clock elements) (D) +0 Year S.DATERD Month Reading S.DATERD D data of the Page Hour Minute expansion Sec. clock SP.DATERD Day of the week SP.DATERD D 1/1000 sec. (S1) (S2) S.DATE+ S.DATE+ S1 S2 D Hour...
Page 78: Program Control Instructions
2.5.17 Program control instructions Execution Category Symbol Processing Details Condition PSTOP PSTOP File name • Places designated program in standby Page status. PSTOPP PSTOPP File name POFF • Turns OUT instruction coil of POFF File name Page designated program OFF, and places POFFP POFFP File name...
Page 79 Execution Category Symbol Processing Details Condition ZRRDB Lower 8 bits ZRRDB Upper 8 bits Page Lower 8 bits Upper 8 bits ZRRDBP ZRRDBP 8 bits ZRWRB Lower 8 bits Direct read/write ZRWRB Upper 8 bits Page operations in 1- Lower 8 bits byte units Upper 8 bits ZRWRBP...
Page 80 Execution Category Symbol Processing Details Condition Reading data S.DEVLD S.DEVLD n1 • Reads data from the device data Page from standard storage file in the standard ROM. SP.DEVLD SP.DEVLD n1 • Transfers the program stored in a Loading program memory card or standard memory Page PLOADP PLOADP...
Page 81: Instructions For Data Link
Instructions for Data Link 2.6.1 Instructions for Network refresh Execution Category Symbol Processing Details Condition S.ZCOM S.ZCOM Link SP.ZCOM SP.ZCOM Jn instruction: Page Refreshes the designated network. Network S.ZCOM S.ZCOM refresh SP.ZCOM SP.ZCOM Un 2.6.2 Instructions for Reading/Writing Routing Information Execution Category Symbol...
Page 82: Multiple Cpu Dedicated Instruction
Multiple CPU dedicated instruction 2.7.1 Instructions for Writing to the CPU Shared Memory of Host CPU Execution Category Symbol Processing Details Condition S. TO S.TO • Writes device data of the host station to the Page host CPU shared memory. SP.
Page 83: Multiple Cpu High-Speed Transmission Dedicated Instruction
Multiple CPU high-speed transmission dedicated instruction 2.8.1 Instructions for Multiple CPU high-speed transmission Execution Category Symbol Processing Details Condition In multiple CPU system, data stored in a Writing D.DDWR D.DDWR device specified by host CPU ( ) or later is Devices to Page stored by the number of write points specified...
Page 84: Chapter 3 Configuration Of Instructions
CHAPTER 3 CONFIGURATION OF INSTRUCTIONS Configuration of Instructions Most CPU module instructions consist of an instruction part and a device part. Each part is used for the following purpose: • Instruction part..indicates the function of the instruction. • Device part...indicates the data that is to be used with the instruction. The device part is classified into source data, destination data, and number of devices.
Page 85: Designating Data
Designating Data The following six types of data can be used with CPU module instructions..Page 83, Section 3.2.1 Bit data Data that can be handled by CPU module ...Page 84, Section 3.2.2 Numeric data Word data Integer data ...Page 85, Section 3.2.3 Double-word data Real number ...Page 88,...
Page 86: Using Word (16 Bits) Data
3.2.2 Using word (16 bits) data Word data is 16-bit numeric data used by basic instructions and application instructions. The following two types of word data can be used with CPU module: • Decimal constants....K-32768 to K32767 • Hexadecimal constants..H0000 to HFFFF Word devices and bit devices designated by digit can be used as word data.
Page 87: Using Double Word Data (32 Bits)
(d) In cases where digit designation is made at the destination (D), the number of points designated are used as the destination. Bit devices below the number of points designated as digits do not change. Ladder Example Processing When source (S) data is a numerical value H1234 0 0 0 1 1 0 1 0 0 X010...
Page 88 (1) When Using Bit Devices (a) Digit designation can be used to enable a bit device to deal with double word data. Digit designation of bit devices is done by designating Number of digits Head number of bit device " ".
Page 89 (d) In cases where digit designation is made at the destination (D), the number of points designated are used as the destination. Bit devices below the number of points designated as digits do not change. Ladder Example Processing When source (S) data is a numerical value H78123456 0 0 1 1 DMOV H78123456 K5M0...
Page 90: Using Real Number Data
3.2.4 Using real number data Real number data is floating decimal point data used with basic instructions and application instructions. Only word devices are capable of storing real number data. (1) Single-precision floating-point data Instructions which deal with single-precision floating-point data designate devices which are used for the lower 16 bits of data.
Page 91 Remark In sequence programs, floating decimal point data are designated by E Double-precision floating-point data uses four word devices and is expressed in the following manner: [Exponent part] [Sign] 1. [Mantissa part] 2 The bit configuration and meaning of the internal representation of double-precision floating-point data is as follows: b52 to b62 b0 to 51...
Page 92: Using Character String Data
3.2.5 Using character string data Character string data is character data used by basic instructions and application instructions. The target ranges from the designated character to the NULL code (00 ) that indicates the end of the character string. (1) When designated character is the NULL code One word is used to store the NULL code.
Page 93: Indexing
Indexing (1) Overview of indexing (a) Indexing is an indirect setting made by using an index register. When an Indexing is used in a sequence program, the device to be used will become the device number specified directly plus the contents of the index register. For example, if D2Z2 has been specified, the specified device is calculated as follows: D(2+3) = D5 and the content of Z2 is 3 become the specified device.
Page 94 Remark For timer and counter present values, there are no limits on index register numbers used. Value set for timer K100 Present value of timer SM400 T0Z4 K4Y30 Value set for counter C100 Present value of counter SM400 C100Z6 K2Y40 (c) A case where Indexing has been performed, and the actual process device, would be as follows: (When Z0 20 and Z1...
Page 95 (a) Example of specifing the range of index registers for use of 32-bit indexing. 1) Each index register can be set between -2147483648 and 2147483647. An example of indexing is shown below. Stores 40000 at Z0. DMOV K40000 Stores the data of ZR10Z0= ZR10Z0 ZR{10+40000}=ZR40010 at D0.
Page 96 5) An example of indexing and the actual process device are as follows. (When Z0 (32-bit) 100000 and Z2 (16-bit) -20) Ladder Example Actual Process Device DMOV K100000 ZR101000 D10 K-20 Description ZR1000Z0 ZR(1000+100000)=ZR101000 D30Z2 D(30-20)=D10 ZR1000Z0 D30Z2 Fig. 3.9 Ladder Example and Actual Process Device (b) Example of specifing 32-bit indexing with “ZZ”...
Page 97 4) Usable range of index registers The following table shows the usable range of index registers in 32-bit indexing used “ZZ” specification. The 32-bit indexing with “ZZ” specification is specified as the format ZRmZZn. Specifying ZRmZZn enables Zn and Zn+1 of 32-bit values to index the device number, ZRm, Index Registers Used Index Registers Used “ZZ”...
Page 98 (4) Index modification using extended data register (D) and extended link register (W) (Universal model QCPU (excluding Q00UJCPU) and LCPU) Like index modification using data register (D) and link register (W) of internal user device, a device can be specified by index modification within the range of the extended data register (D) and extended link register (W).
Page 99 2) Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) will not cause an error.
Page 100 (c) Both network numbers and device numbers can be performed indexing with link direct devices* MOV J1Z1\K4X0Z2 D0 If Z1=2 and Z2=8, then J(1+2)\K4X(0+8)=J3\K4X8 *1: For the intellingent function module device, link direct devices, refer to the QnUCPU User’s Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manual (Function Explanation, Program Fundamentals) (d) When indexing is used for multiple CPU shared devices* , indexing for the head I/O numbers of CPU modules and...
Page 101 (b) Performing indexing with the CALL instruction Pulses can be output with the CALL instruction by use of the edge relay (V). However, pulse output using the PLS/ PLF/pulse ( P) instruction is not allowed. [When edge relay is used] [When edge relay is not used] (M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.)
Page 102: Indirect Specification
Indirect Specification (1) Indirect Specification (a) Indirect specification is a method that specifies address of the device to be used in a sequence program using two word devices (two points of word device). Use indirect specification as index modification when the index register is insufficient.
Page 103 (3) Precautions (a) The address for indirect specification uses two words. Therefore, to substitute indirect specification for index modification, the addition/subtraction of 32-bit data is required. The following is the ladder used for the address addition/subtraction of the device stored in D1 and D0 for indirect specification. [To add "1"...
Page 104: Reducing Instruction Processing Time
Reducing Instruction Processing Time 3.5.1 Subset Processing Subset processing is used to place limits on bit devices used by basic instructions and application instructions in order to increase processing speed. However, the instruction symbol does not change. To shorten scans, run instructions under the conditions indicated below. (1) Conditions which each device must meet for subset processing (a) When using word data Device...
Page 105: (Universal Model Qcpu And Lcpu Only)
(2) Instructions for which subset processing can be used Types of Instructions Instruction Symbols Contact instructions LD,LDI,AND,ANI,OR,ORI,LDP,LDF,ANDP,ANDF,ORP,ORF,LDPI,ANDPI,ANDFI,ORPI,ORFI Output instructions OUT,SET,RST Comparison operation instruction • • +,-,*,/,INC,DEC,D+,D-,D*,D/,DINC,DDEC Arithmetic operation • B+,B-,B*,B/, E+,E-,E*,E/ Data conversion instructions • BCD, BIN, DBCD, DBIN, FLT, DFLT, INT, DINT •...
Page 106: Cautions On Programming (Operation Errors)
Cautions on Programming (Operation Errors) Operation errors are returned in the following cases when executing basic instructions and application instructions with CPU module: • An error listed on the explanatory page for the individual instruction occurred. • When an intelligent function module device is used, no intelligent function module is installed at the specified I/O number position.
Page 107 2) Universal model QCPU and LCPU The device range is checked. When the device number is outside the device range, an operation error occurs. For example, when12 k points are assigned to a data register, an error occurs if the device number of the data register exceeds D12287.
Page 108 The device range is checked even though indexing is executed. An error occurs when the head device number of the devices with indexing exceeds the device range. BMOV D12285Z1 K2 When D12287 is specified with the BMOV instruction, the target devices are D12287 and D12288. However, an operation error occurs because D12288 BMOV D12287Z1 K2...
Page 109 4) Access to file registers (R, ZR) exceeded the range of file register files Presetting PC parameter not to check indexing device range enables the Universal model QCPU not to detect an error in the above accesses from 1) to 4). Detecting an error in the above accesses from 1) to 4) , however, depends on the serial No.
Page 110 (2) Device data check Device data checks for the devices used by basic instructions and application instructions in CPU module are as indicated below: (a) When using BIN data No error is returned even if the operation results in overflow or underflow. The carry flag does not go on at such times, either.
Page 111: Conditions For Execution Of Instructions
Conditions for Execution of Instructions The following four types of execution conditions exist for the execution of CPU module sequence instructions, basic instructions, and application instructions: • Non-conditional execution...Instructions executed without regard to the ON/OFF status of the device Example LD X0, OUT Y10 •...
Page 112: Counting Step Number
Counting Step Number The number of steps in CPU module sequence instructions, basic instructions, and application instructions differs depending on whether indirect setting of the device used is possible or not. (1) Counting the number of basic steps The basic number of steps for basic instructions and application instructions is calculated by adding the device number and 1.
Page 113 Added Steps Basic Number Instruction Symbols Devices with Additional Steps (Number of of Steps Instruction Steps) Serial number access format file register, Extended data register (D), ANDPI,ANDFI,ORPI,ORFI 1(5) Extended link register (W) Multiple CPU shared device* Serial number access format file register Extended data register (D), 1(2) Extended link register (W)
Page 114 Added Steps Basic Number Instruction Symbols Devices with Additional Steps (Number of of Steps Instruction Steps) Serial number access format file register Extended data register (D), D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR, Extended link register (W) DANDP,DORP,DXORP,DXNRP Multiple CPU shared device* (3 devices)* Decimal constant, hexadecimal constant, real constant Serial number access format file register Extended data register (D),...
Page 115 When multiple standard device registers are used in an instruction applicable to subset processing, the number of steps decreases. The following table shows the number of steps for each instruction. Added Steps Locations Where Standard Device Basic Number Instruction Symbols (Number of Register Is Used of Steps...
Page 116 2) Except Instructions applicable to subset processing The following table shows steps depending on the devices. Devices with Additional Steps Added Steps Example Intelligent function module device MOV U4\G10 D0 Multiple CPU shared device MOV U3E1\G10000 D0 Link direct device MOV J3\B20 D0 Index register / standard device register MOV Z0 D0...
Page 117: Operation When The Out, Set/Rst, Or Pls/Plf Instructions Use The Same Device
Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device The following describes the operation for executing multiple instructions of the OUT, SET/RST, or PLS/PLF that use the same device in one scan. (1) OUT instructions using the same device Do not program more than one OUT instruction using the same device in one scan.
Page 118 (c) When the SET instruction and RST instruction using the same device are programmed in one scan, the SET instruction turns ON the specified device when the SET execution command is ON and the RST instruction turns OFF the specified device when the RST execution command is ON. When both the SET and RST execution commands are OFF, the ON/OFF status of the specified device will not be changed.
Page 119 [Timing Chart] • The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON throughout the scan.) M0 turns ON because X1 M0 turns OFF because X1 goes ON (OFF ON). status is other than OFF M0 turns OFF because X0 status M0 turns ON because is other than OFF...
Page 120 [Ladder] [Timing Chart] • The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON throughout the scan.) M0 turns OFF because X1 status is M0 turns OFF because X1 other than ON OFF. status is other than ON OFF.
Page 121: Precautions For Use Of File Registers
3.10 Precautions for Use of File Registers This section explains the precautions for use of the file registers in the QCPU and LCPU. (1) CPU modules that cannot use file registers The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers, use the CPU module of other than the Q00JCPU and Q00UJCPU.
Page 122 (5) File register specifying method There are the block switching method and serial number access method to specify the file registers. (a) Block switching method In the block switching method, specify the number of used file register points in units of 32k points (one block). For file registers of 32k points or more, specify the file registers by switching the block No.
Page 123 (b) Restrictions The restrictions when specifying file registers to refresh devices are as follows. 1) On QCPU, Refresh cannot be performed correctly if the use of file register which has the same name as the program is specified by the PLC parameter. When the file register which has the same name as the program is used, refresh is performed to the data of the file register having the same name as the program that is set at the last number in the [Program] tab page of PLC parameter.
Page 124: Chapter 4 How To Read Instructions
CHAPTER 4 HOW TO READ INSTRUCTIONS The description of instructions that are contained in the following chapters are presented in the following format. 1) Code used to write instruction (instruction symbol). 2) Section number described. 3) Shows if instructions are enabled or disabled for each CPU module type. Icon Basic High...
Page 125 4) Indicates ladder mode expressions and execution conditions for instructions. Non- Executed One Time Executed One Execution Condition conditional Executed while ON Executed while OFF at ON Time at OFF Execution Code recorded on No symbol description page recorded 5) Indicates the data set for each instruction and the data type. Data Type Meaning Bit data or head number in bit data...
Page 126: Chapter 5 Sequence Instructions
LD, LDI, AND, ANI, OR, ORI CHAPTER 5 SEQUENCE INSTRUCTIONS Contact Instructions 5.1.1 LD, LDI Operation start 5.1.1 AND, ANI Series connection OR, ORI Parallel connection LD, LDI, AND, ANI, OR, ORI High Basic Process Redundant Universal LCPU performance Bit device number / Word device bit designation ( X1/D0.1 X1/D0.1 X2/D0.2...
Page 127: And, Ani
LD, LDI, AND, ANI, OR, ORI AND, ANI (1) AND is the A contact series connection instruction, and ANI is the B contact series connection instruction. They read the ON/OFF data of the designated bit device* , perform an AND operation on that data and the operation result to that point, and take this value as the operation result.
Page 128: Pulse Operation Start
LDP, LDF, ANDP, ANDF, ORP, ORF (2) A program linking contacts using the ANB and ORB instructions. [Ladder Mode] [List Mode] Device Step Instruction Bit designated for word device (3) A parallel program with the OUT instruction. [Ladder Mode] [List Mode] Instruction Device Step...
Page 129: Ldp, Ldf
LDP, LDF, ANDP, ANDF, ORP, ORF Function LDP, LDF (1) LDP is the leading edge pulse operation start instruction, and is ON only at the leading edge of the designated bit device (when it goes from OFF to ON). If a word device has been designated, it is ON only when the designated bit changes from 0 to 1.
Page 130: Pulse Not Operation Start
LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI Operation Error (1) There is no operation error in the LDP, LDF, ANDP, ANDF, ORP, or ORF instruction. Program Example (1) The following program executes the MOV instruction at input X0, or at the leading edge of b10 (bit 11) of data register [Ladder Mode] [List Mode] Instruction...
Page 131: Ldpi, Ldfi
LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI Function LDPI, LDFI (1) LDPI is the leading edge pulse NOT operation start instruction that is on only at the leading edge of the specified bit device (when the bit device goes from on to off) or when the bit device is on or off. If a word device has been specified, LDPI is on only when the specified bit is 0, 1, or changes from 1 to 0.
Page 132 LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI Program Example (1) The following program stores 0 into D0 when X0 is on, off, or turns from on to off, or M0 is on, off, or turns from off to on. [Ladder Mode] [List Mode] Instruction Device...
Page 133: Association Instructions
ANB, ORB Association Instructions 5.2.1 Ladder block series connection 5.2.1 Ladder block parallel connection ANB, ORB High Basic Process LCPU Redundant Universal performance Block A Block B Block A Block B For parallel connection of 1 contact, OR or ORI is used. Setting Internal Devices R, ZR...
Page 134: Mps
MPS, MRD, MPP Operation Error (1) There is no operation error in the ANB or ORB instruction. Program Example (1) A program using the ANB and ORB instructions. [Ladder Mode] [List Mode] Step Instruction Device 5.2.2 Operation results push 5.2.2 Operation results read Operation results pop MPS, MRD, MPP...
Page 135 MPS, MRD, MPP 1. The following shows ladders both using and not using the MPS, MRD, and MPP instructions. Ladder Using the MPS, MRD and MPP Instructions Ladder not Using MPS, MRD, and MPP Instructions 2. The MPS and MPP instructions must be used the same number of times. Failure to observe this will not correctly display the ladder in the ladder mode of the peripheral device.
Page 136 MPS, MRD, MPP (2) A program using the MPS and MPP instructions successively. [Ladder Mode] [List Mode] Instruction Device Step...
Page 137: Inv
5.2.3 Operation results inversion 5.2.3 High Basic Process LCPU Redundant Universal performance Command Setting Internal Devices R, ZR Constants Other Data Word Word –– –– Function Inverts the operation result immediately prior to the INV instruction. Operation Result Immediately Prior to Operation Result Following the the INV Instruction Execution of the INV Instruction...
Page 138: Mep, Mef
MEP, MEF 5.2.4 MEP, MEF Operation results conversion 5.2.4 MEP, MEF High Basic Process Redundant Universal LCPU performance Command Command Setting Internal Devices R, ZR Constants Other Data Word Word –– –– Function (1) If operation results up to the MEP instruction are leading edge (from OFF to ON), goes ON (continuity status). If operation results up to the MEP instruction are anything other than leading edge, goes OFF (non-continuity status).
Page 139: Egp, Egf
EGP, EGF 5.2.5 EGP, EGF Pulse conversion of edge relay operation results 5.2.5 EGP, EGF High Basic Process LCPU Redundant Universal performance Command Command : Edge relay number where operation results are stored (bits) Setting Internal Devices Other R, ZR Constants Data Word...
Page 140 EGP, EGF Program Example (1) A program using the EGP instruction in the subroutine program using the EGD instruction [Ladder Mode] [List Mode] Step Instruction Device [Operation] END processing Turns OFF as X0 remains ON. Turns ON at the leading Turns OFF as X1 remains ON.
Page 141: Output Instructions
Output Instructions 5.3.1 Out (excluding timers, counters, and annunciators) 5.3.1 High Basic Process LCPU Redundant Universal performance Bit device number ( Command Word device Command bit designation ( D0.5 : Number of the device to be turned ON and OFF (bits) Setting Internal Devices Other...
Page 142 (2) When bit designation has been made for word device [Ladder Mode] [List Mode] Instruction Device Step Remark The number of basic steps for the OUT instructions is as follows: • When using internal device or file register (R): 1 •...
Page 143: Out T
OUT T, OUTH T, OUT ST, OUTH ST 5.3.2 OUT T Low-speed timer OUTH T High-speed timer 5.3.2 OUT ST Low-speed retentive timer OUTH ST High-speed retentive timer OUT T, OUTH T, OUT ST, OUTH ST High Basic Process Redundant Universal LCPU performance Command...
Page 144 OUT T, OUTH T, OUT ST, OUTH ST (2) The contact responds as follows when the operation result up to the OUT instruction is a change from ON to OFF: Present Value Prior to Time Up After Time Up Type of Timer Timer Coil of Timer A Contact...
Page 145 OUT T, OUTH T, OUT ST, OUTH ST Caution (1) When creating a program in which the operation the timer contact triggers the operation of other timer, create the program for the timer that operates later first. In the following cases, all timers go ON at the same scan if the program is created in the order the timers operate. •...
Page 146: Out C
OUT C (2) The following program uses the BCD data at X10 to X1F as the timer's set value. [Ladder Mode] Converts the BCD data at X10 to X1F to BIN and stores the converted value at D10. When X2 is turned ON, T2 starts measurement using the data stored in D10 as the set value.
Page 147 OUT C Function (1) When the operation results up to the OUT instruction change from OFF to ON, 1 is added to the present value (count value) and the count up status (present value set value), and the contacts respond as follows: A Contact Continuity B Contact...
Page 148: Out F
OUT F [List Mode] Instruction Device Step 5.3.4 OUT F Annunciator output 5.3.4 OUT F High Basic Process LCPU Redundant Universal performance Annunciator number Command OUT F : Number of the annunciator to be turned ON (bits) Setting Internal Devices R, ZR Constants Other...
Page 149: Set
Program Example (1) The following program turns F7 ON when X0 goes ON, and stores the value 7 from SD64 to SD79. [Ladder Mode] [List Mode] Step Instruction Device [Operation] X0 ON Adds 1 SD63 SD63 SD64 SD64 SD65 SD65 SD66 SD66 SD67...
Page 150: Rst
Operation Error (1) There is no operation error in the SET instruction. Program Example (1) The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9 goes ON. [Ladder Mode] [List Mode] Instruction Device Step (2) The following program sets the value of D0 bit 5 (b5) to 1 when X8 goes ON, and set the bit value to 0 when X9 goes ON.
Page 151 Function (1) When the execution command is turned ON, the status of the designated devices becomes as shown below: Device Device Status Bit device Turns coils and contacts OFF Timers and counters Sets the present value to 0, and turns coils and contacts OFF When Bit Designation has been Made for Word Device Sets value of designated bit to 0 Word devices other than timers and counters...
Page 152: Setting Annunciators
SET F, RST F (2) The following program resets the 100 ms retentive timer and counter. [Ladder Mode] When ST225 is set as retentive timer, it is turned ON when X4 ON time reaches 30 min. Counts the number of times ST225 was turned ON.
Page 153: Set F
SET F, RST F Remark 1. For details of annunciators, refer to the User's Manual (Functions Explanatio Program Fundamentals) for the CPU module used. 2. The number of basic steps for the SET F and RST F instructions is 2. (3) When the value of SD63 is "16", the annunciator numbers are deleted from SD64 to SD79 by the use of the RST instruction.
Page 154: Pls
PLS, PLF 5.3.8 Leading edge output 5.3.8 Trailing edge output PLS, PLF High Basic Process LCPU Redundant Universal performance Command Command : Pulse conversion device (bits) Setting Internal Devices Other R, ZR Constants Data Word Word –– Function (1) Turns ON the designated device when the execution command is turned OFF ON, and turns OFF the device in any other case the execution command is turned OFF ON (i.e., at ON...
Page 155 PLS, PLF (1) Turns ON the designated device when the execution command is turned ON OFF, and turns OFF the device in any other case the execution command is turned ON OFF (i.e., at OFF OFF, OFF ON or ON ON of the execution command).
Page 156: Ff Bit Device Output Inversion
[Timing Chart] X9 OFF M9 OFF 1 scan 5.3.9 Bit device output inversion 5.3.9 High Basic Process LCPU Redundant Universal performance Command : Device number of the device to be reversed (bits) Setting Internal Devices Other R, ZR Constants Data Word Word ––...
Page 157: Delta, Deltap
DELTA, DELTAP (2) The following program reverses b10 (bit 10) of D10 when X0 goes ON. [Ladder Mode] [List Mode] Step Instruction Device [Timing Chart] D10 of b10 5.3.10 DELTA, DELTAP Pulse conversion of direct output 5.3.10 DELTA, DELTAP High Basic Process LCPU...
Page 158 DELTA, DELTAP Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified direct access output number exceeds the CPU module 4101 output range.
Page 159: Shift Instructions
SFT, SFTP Shift Instructions 5.4.1 SFT, SFTP Bit device shift 5.4.1 SFT, SFTP High Basic Process Redundant Universal LCPU performance Command Command SFTP SFTP : Device number to shift (bits) Internal Devices Setting Other R, ZR Constants Data Word Word ––...
Page 160 SFT, SFTP Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The points of the specified device exceed those of the corresponding 4101 device.
Page 161: Master Control Instructions
MC, MCR Master Control Instructions 5.5.1 Setting the master control 5.5.1 Resetting the master control MC, MCR High Basic Process LCPU Redundant Universal performance Command Master control ladder : Nesting (N0 to N14) (Nesting) : Device number to be turned ON (bits) Setting Internal Devices Other...
Page 162 MC, MCR (1) If the execution command of the MC instruction is ON when master control is started, the result of the operation from the MC instruction to the MCR instruction will be exactly as the instruction (ladder) shows. If the execution command of the MC instruction is OFF, the result of the operation from the MC instruction to the MCR instruction will be as shown below: Device Device Status...
Page 163 MC, MCR Program Example The master control instruction can be used in nesting. The different master control regions are distinguished by nesting (N). Nesting can be performed from N0 to N14. The use of nesting enables the creation of ladders which successively limit the execution condition of the program. A ladder using nesting would appear as shown below: [Ladder as displayed in the GPP ladder mode] [Ladder as it actually operates]...
Page 164 MC, MCR Cautions when Using Nesting Architecture (1) Nesting can be used up to 15 times (N0 to N14) When using nesting, nests should be inserted from the lower to higher nesting number (N) with the MC instruction, and from the higher to the lower order with the MCR instruction. If this order is reversed, there will be no nesting architecture, and the CPU module will not be capable of performing correct operations.
Page 165: Termination Instructions
FEND Termination Instructions 5.6.1 FEND Main routine program end 5.6.1 FEND High Basic Process LCPU Redundant Universal performance FEND FEND Setting Internal Devices R, ZR Constants Other Data Word Word –– –– Function (1) The FEND instruction is used in cases where the CJ instruction or other instructions are used to cause a branch in the sequence program operations, and in cases where the main routine program is to be split from a subroutine program or an interrupt program.
Page 166 FEND Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The FEND instruction was executed after the execution of the FOR 4200 instruction, and before the execution of the NEXT instruction.
Page 167: End
5.6.2 Sequence program end 5.6.2 High Basic Process LCPU Redundant Universal performance Setting Internal Devices R, ZR Constants Other Data Word Word –– –– Function (1) Indicates termination of programs, including main routine program, subroutine program, and interrupt programs. Execution of the END instruction will cause the CPU module to terminate the program that was being executed. Sequence program (2) The END instruction cannot be used during the execution of the main sequence program.
Page 168 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The END instruction was executed before the execution of the NEXT 4200 instruction and after the execution of the FOR instruction.
Page 169: Other Instructions
STOP Other instructions 5.7.1 STOP Sequence program stop 5.7.1 STOP High Basic Process LCPU Redundant Universal performance Command STOP STOP Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Resets the output (Y) and stops the CPU module operation when the execution command is turned ON. (The same result will take place if switch is turned to the STOP setting.) (2) Execution of the STOP instruction will cause the value of b4 to b7 of the special register SD203 to become "3".
Page 170: Nop, Noplf, Page N
NOP, NOPLF, PAGE n Program Example (1) The following program stops the CPU module when X8 goes ON. [Ladder Mode] Stops the programmable controller when X8 goes ON. Sequence program [List Mode] Step Instruction Device 5.7.2 NOP, NOPLF, PAGE n No operations 5.7.2 NOP, NOPLF, PAGE n High...
Page 171 NOP, NOPLF, PAGE n NOPLF (1) This is a no operation instruction that has no impact on any operations up to that point. (2) The NOPLF instruction is used when printing from a peripheral device to force a page change at any desired location. (a) When printing ladders •...
Page 172 NOP, NOPLF, PAGE n (2) Contact closed ... LD, LDI changed to NOP. (Note carefully that changing the LD and LDI instructions to NOP completely changes the nature of the ladder.) [Ladder Mode] [List Mode] Before change Instruction Device Step Step Instruction Device...
Page 173 NOP, NOPLF, PAGE n • Printing the ladder will result in the following: NOPLF instruction, inserted as a delimiter NOPLF of ladder blocks, causes print out page to be changed forcibly. • Printing an instruction list with the NOPLF instruction will result in the following: NOPLF Changes print output page after printing NOPLF.
Page 174: Chapter 6 Basic Instructions
=, <>, >, <=, <, >= CHAPTER 6 BASIC INSTRUCTIONS Comparison Operation Instructions 6.1.1 =, <>, >, <=, <, >= BIN 16-bit data comparisons 6.1.1 =, <>, >, <=, <, >= High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command Command Command...
Page 175: Bin 32-Bit Data Comparisons
D=, D<>, D>, D<=, D<, D>= Program Example (1) The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON if the data is identical. [Ladder Mode] [List Mode] Instruction Device Step (2) The following program compares BIN value K100 to the data at D3, and establishes continuity if the data in D3 is something other than 100.
Page 176 D=, D<>, D>, D<=, D<, D>= Function (1) Treats BIN 32-bit data from device designated by and BIN 32-bit data from device designated by as an a normally- open contact, and performs comparison operation. (2) The results of the comparison operations for the individual instructions are as follows: Instruction Comparison Instruction...
Page 177: Floating-Point Data Comparisons (Single Precision)
E=, E<>, E>, E<=, E<, E>= (4) The following program compares the data in D0 and D1 with the data in D3 and D4, and establishes continuity if the data in D0 and D1 is equal to or less than the data in D3 and D4. [Ladder Mode] [List Mode] Device...
Page 178 E=, E<>, E>, E<=, E<, E>= Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100...
Page 179: Ed=, Ed<>, Ed>, Ed<=, Floating-Point Data Comparisons (Double Precision)
ED=, ED<>, ED>, ED<=, ED<, ED>= 6.1.4 ED=, ED<>, ED>, ED<=,Floating-point data comparisons (Double precision) ED<, ED>= 6.1.4 ED=, ED<>, ED>, ED<=, ED<, ED>= High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of ED Command Command Command : Data for comparison or head number of the devices where the data for comparison is stored (real number) Internal Devices Setting...
Page 180 ED=, ED<>, ED>, ED<=, ED<, ED>= Program Example (1) The following program compares 64-bit floating decimal point real number data at D0 to D3 with 64-bit floating decimal point real number data at D4 to D7. [Ladder Mode] [List Mode] Device Step Instruction...
Page 181: Character String Data Comparisons
$=, $<>, $>, $<=, $<, $>= Example When judging the mismatch of E1.234567890123456+10 (Number of significant digits is 16) and the double-precision floating-point data. E1.234567890123456+10 E1.23456789012345+10 E1.23456789012346+10 Whether D0 to D3 is within this range is checked.(Values on boundaries are included.) 6.1.5 $=, $<>, $>, $<=, $<, Character string data comparisons...
Page 182 $=, $<>, $>, $<=, $<, $>= (b) If the character strings are different, the character string with the larger character code will be the larger. "ABCDF" "ABCDE" Comparison Operation Result Comparison Operation Result Instruction Symbol in Instruction Symbol in Non-continuity $<= Non-continuity $<>...
Page 183 $=, $<>, $>, $<=, $<, $>= The character string data comparison instruction checks the device range while comparing the designated character string data. For this reason, if the "00 " code does not exist in the relevant device range, the instruction outputs the comparison result instead of returning an operation error when no match of characters is detected.
Page 184: Bkcmp , Bkcmpp
BKCMP , BKCMP P 6.1.6 BKCMPooo, BKCMPoooPBIN 16-bit block data comparisons 6.1.6 BKCMP , BKCMP P High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command BKCMP BKCMP Command BKCMP BKCMP : Data to be compared or head number of the devices where the data to be compared is stored (BIN 16 bits) : Head number of the devices where the comparison data is stored (BIN 16 bits) : Head number of the devices where the comparison operation result will be stored (bits) : Number of comparison data blocks (BIN 16 bits)
Page 185 BKCMP , BKCMP P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The points specified in n exceeds those of each device specified in , or The ranges of devices starting from the one specified in...
Page 186: Dbkcmp
DBKCMP , DBKCMP P (3) The following program compares, when X20 is turned ON, the data at D10 to D12 with the data at D30 to D32, and stores the operation result into the area starting from M100. The following program transfers the character string "ALL ON" to D100 onward when all devices from M100 onward have reached the 1 "ON"...
Page 187 DBKCMP , DBKCMP P Function (1) This instruction compares BIN 32-bit data stored in n-point devices starting from the device specified by with BIN 32- bit data stored in n-point devices starting from the device specified by a constant and and then stores the result into the nth device specified by and up.
Page 188 DBKCMP , DBKCMP P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 A negative value is specified for n.
Page 189 DBKCMP , DBKCMP P When certain bits are specified in a word device, bits other than the certain bits that store the operation result do not change. D10.F D10.0 Before execution D10.F D10.0 After execution No change No change (3) The following program compares the value data stored at D0 to D5 with the value data stored at D10 to D15, and then stores the operation result into M20 to M22, when M0 is turned on.
Page 190: Arithmetic Operation Instructions
+, +P, -, -P Arithmetic Operation Instructions 6.2.1 +, +P, -, -P BIN 16-bit addition and subtraction operations 6.2.1 +, +P, -, -P High Basic Process Redundant Universal LCPU performance When two data are set ( indicates an instruction symbol of Command Command +P, P...
Page 191 +, +P, -, -P (4) The following will happen when an underflow or overflow is generated in an operation result: The carry flag in this case does not go ON. Since bit 15 value is "0", K32766 K 32768 (8000 (0002 (7FFE result of operation takes a positive value.
Page 192 +, +P, -, -P – (1) Subtracts 16-bit BIN data designated by from 16-bit BIN data designated by and stores the result of the subtraction at the device designated by 5678 (BIN) 1234 (BIN) 4444 (BIN) (2) Values for can be designated between -32768 and 32767 (BIN, 16 bits).
Page 193: Bin 32-Bit Addition And Subtraction Operations
D+, D+P, D-, D-P 6.2.2 D+, D+P, D-, D-P BIN 32-bit addition and subtraction operations 6.2.2 D+, D+P, D-, D-P High Basic Process Redundant Universal LCPU performance When two data are set (( +1, )+( +1, ) ( +1, ), ( +1, )-( +1, ) ( +1, )) indicates an instruction symbol of Command D+, D...
Page 194 D+, D+P, D-, D-P (4) The following will happen when an underflow or overflow is generated in an operation result: The carry flag in this case does not go ON. Since bit 31 value is "0", K 2147483648 K2 K2147483646 (80000000 (00000002 (7FFFFFFE...
Page 195 D+, D+P, D-, D-P (1) Subtracts 32-bit BIN data designated by from 32-bit BIN data designated by and stores the result of the subtraction at the device designated by b16 b15 b16 b15 b16 b15 567890 (BIN) 123456 (BIN) 444434 (BIN) (2) The values for can be designated at between -2147483648 and 2147483647 (BIN 32 bits).
Page 196: Bin 16-Bit Multiplication And Division Operations
*, *P, /, /P 6.2.3 *, *P, /, /P BIN 16-bit multiplication and division operations 6.2.3 *, *P, /, /P High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of * Command *, / Command *P, / P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 16 bits) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 16 bits) : Head number of the devices where the multiplication/division operation result will be stored (BIN 32 bits)
Page 197 *, *P, /, /P (1) Divides BIN 16-bit data designated by and BIN 16-bit data designated by , and stores the result in the device designated by Quotient Remainder 5678 (BIN) 1234 (BIN) 4 (BIN) 742 (BIN) (2) If a word device has been used, the result of the division operation is stored as 32 bits, and both the quotient and remainder are stored;...
Page 198: Bin 32-Bit Multiplication And Division Operations
D*, D*P, D/, D/P 6.2.4 D*, D*P, D/, D/P BIN 32-bit multiplication and division operations 6.2.4 D*, D*P, D/, D/P High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command D*, D/ Command D*P, D/P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 32 bits) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 32 bits) : Head number of the devices where the multiplication/division operation result will be stored (BIN 64 bits) Setting...
Page 199 D*, D*P, D/, D/P (1) Divides BIN 32-bit data designated by and BIN 32-bit data designated by , and stores the result in the device designated by b31 b16 b31 b16 b31 b16 567890 (BIN) 123456 (BIN) 4 (BIN) 74066 (BIN) (2) With a word device, the division operation result is stored in 64 bits and both the quotient and remainder are stored.
Page 200: Bcd 4-Digit Addition And Subtraction Operations
B+, B+P, B-, B-P 6.2.5 B+, B+P, B-, B-P BCD 4-digit addition and subtraction operations 6.2.5 B+, B+P, B-, B-P High Basic Process Redundant Universal LCPU performance When two data are set ( B+/B indicates an instruction symbol of Command B+, B Command B+P, B P...
Page 201 B+, B+P, B-, B-P Program Example (1) The following program adds BCD data 5678 and 1234, stores it at D993, and at the same time outputs it to from Y30 to Y3F. [Ladder Mode] Stores 5678 in BCD to D993. Adds 1234 in BCD to the value at D993, and stores the result to D993.
Page 202 B+, B+P, B-, B-P Function (1) Adds the BCD 4-digit data designated by and the BCD 4-digit data designated by , and stores the result of the addition at the device designated by (2) 0 to 9999 (BCD 4 digits) can be assigned to S1 S2 (3) If the result of the addition operation exceeds 9999, the higher bits are ignored.
Page 203: Bcd 8-Digit Addition And Subtraction Operations
DB+, DB+P, DB-, DB-P 6.2.6 DB+, DB+P, DB-, DB-P BCD 8-digit addition and subtraction operations 6.2.6 DB+, DB+P, DB-, DB-P High Basic Process Redundant Universal LCPU performance When two data are set (( +1, )+( +1, ) ( +1, ), ( +1, )-( +1, ) ( +1, )) indicates an instruction symbol of DB+/DB- Command...
Page 204 DB+, DB+P, DB-, DB-P Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 BCD data is outside the 0 to 99999999 range. Program Example (1) The following program adds the BCD data 12345600 and 34567000, stores the result at D887 and D888, and at the same time outputs them to from Y30 to Y4F.
Page 205 DB+, DB+P, DB-, DB-P When three data are set (( +1, )+( +1, ) ( +1, ), ( +1, )-( +1, ) ( +1, )) indicates an instruction symbol of DB+/ DB Command DB+, DB- Command DB+P, DB-P : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits) : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits) : Head number of the devices where the addition/subtraction operation result is stored (BCD 8 digits) Setting...
Page 206: Bcd 4-Digit Multiplication And Division Operations
B*, B*P, B/, B/P Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 BCD data is outside the 0 to 99999999 range. Program Example (1) The following program adds the BCD data at D3 and D4 to the BCD data at Z1 and Z2 when X20 goes ON, and stores the result at R10 and R11.
Page 207 B*, B*P, B/, B/P (1) Divides BCD data designated by and BCD data designated by , and stores the result in the device designated by (Quotient) +1 (Remainder) Digits exceeding the designated number of digits are assumed to be 0. (2) Uses 32 bits to store the result of the division as quotient and remainder Quotient (BCD 4 digits) :Stored at the lower 16 bits.
Page 208: Bcd 8-Digit Multiplication And Division Operations
DB*, DB*P, DB/, DB/P 6.2.8 DB*, DB*P, DB/, DB/P BCD 8-digit multiplication and division operations 6.2.8 DB*, DB*P, DB/, DB/P High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DB* , DB/. Command DB , DB/ Command DB P, DB/P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 8 digits) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 8 digits)
Page 209 DB*, DB*P, DB/, DB/P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code BCD data is outside the 0 to 9999 range.
Page 210: (Single Precision)
E+, E+P, E-, E-P 6.2.9 E+, E+P, E-, E-P Addition and subtraction of floating-point data (Single precision) Ver. High Basic Process LCPU Redundant Universal performance 6.2.9 E+, E+P, E-, E-P • Basic model QCPU: The serial number (first five digits) is "04122"...
Page 211 E+, E+P, E-, E-P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified device value is not within the following range: -126 4100...
Page 212 E+, E+P, E-, E-P When three data are set (( +1, )+( +1, ) ( +1, ), ( +1, )-( +1, ) ( +1, )) indicates an instruction symbol of E+/E-. Command E+, E- Command E+P, E-P : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number) : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) : Head number of the devices where the addition/subtraction operation result is stored (real number) Internal Devices...
Page 213 E+, E+P, E-, E-P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified device value is not within the following range: -126 4100...
Page 214: (Double Precision)
ED+, ED+P, ED-, ED-P 6.2.10 ED+, ED+P, ED-, ED-P Addition and subtraction of floating-point data (Double precision) 6.2.10 ED+, ED+P, ED-, ED-P High Basic Process LCPU Redundant Universal performance When two data are set (( +3, +2, +1, )+( +3, +2, +1, ) ( +3, +2, +1, ), ( +3, +2, +1, )- ( +3, +2, +1, ) ( +3, +2, +1, )) indicates an instruction symbol of ED+/ED-.
Page 215 ED+, ED+P, ED-, ED-P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified device value is not within the following range: -1022 1024...
Page 216 ED+, ED+P, ED-, ED-P When three data are set (( +3, +2, +1, )+( +3, +2, +1, ) ( +3, +2, +1, ), ( +3, +2, +1, )-( +3, +2, +1, ) ( +3, +2, +1, )) indicates an instruction symbol of ED+/ED-. Command ED+, ED- Command...
Page 217 ED+, ED+P, ED-, ED-P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified device value is not within the following range: -1022 1024...
Page 218: (Single Precision)
E*, E*P, E/, E/P 6.2.11 E*, E*P, E/, E/P Multiplication and division of floating-point data (Single precision) Ver. High Basic Process LCPU Redundant Universal performance 6.2.11 E*, E*P, E/, E/P • Basic model QCPU: The serial number (first five digits) is "04122"...
Page 219 E*, E*P, E/, E/P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified device value is not within the following range: -126 ––...
Page 220: (Double Precision)
ED*, ED*P, ED/, ED/P 6.2.12 ED*, ED*P, ED/, ED/P Multiplication and division of floating-point data (Double precision) 6.2.12 ED*, ED*P, ED/, ED/P High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of ED*, ED/. Command ED*, ED/ Command ED* P, ED/P : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (real number) : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (real number)
Page 221 ED*, ED*P, ED/, ED/P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified device value is not within the following range: -1022 1024...
Page 222: Bin 16-Bit Data Block Addition And Subtraction Operations
BK+, BK+P, BK-, BK-P 6.2.13 BK+, BK+P, BK-, BK-P BIN 16-bit data block addition and subtraction operations 6.2.13 BK+, BK+P, BK-, BK-P High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BK+, BK- . Command BK+, BK- Command BK+P, BK-P : Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits)
Page 223 BK+, BK+P, BK-, BK-P (1) Subtracts n points of BIN data from the device designated by and n-points of BIN data from the device designated by and stores the result from the device designated by onward. 8765 (BIN) 1234 (BIN) 7531 (BIN) 8888...
Page 224: Bin 32-Bit Data Block Addition And Subtraction Operations
DBK+, DBK+P, DBK-, DBK-P Program Example (1) The following program adds, when X20 is turned ON, the data stored at D100 to D103 to the data stored at R0 to R3 and stores the operation result into the area starting from D200. [Ladder Mode] [List Mode] Step...
Page 225 DBK+, DBK+P, DBK-, DBK-P Function DBK+ (1) This instruction adds BIN 32-bit data stored in n-point devices starting from the device specified by to BIN 32-bit data stored in n-point devices starting from the device specified by or a constant. and then stores the operation result into the nth device specified by and up, When a device is specified for...
Page 226 DBK+, DBK+P, DBK-, DBK-P specifies out of the range of n-point devices starting from the device specified by However, can specify the same device. (6) The following will happen if an overflow occurs in an operation result: The carry flag in this case is not turned on. K2147483647 ) ( 80000001 (00000002...
Page 227: Linking Character Strings
$+, $+P [Operation] 12345 11111 1234 D101,D100 D51,D50 R101,R100 D103,D102 54321 D53,D52 -11111 R103,R102 65432 D105,D104 D55,D54 R105,R104 -12345 22222 -34567 D107,D106 D57,D56 R107,R106 -54321 -22222 -32099 D109,D108 D58,D58 R109,R108 99999 33333 66666 6.2.15 $+, $+P Linking character strings 6.2.15 $+, $+P High Basic...
Page 228 $+, $+P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The number of device points starting from the device specified in insufficient to store all character strings.
Page 229 $+, $+P Function (1) Links the character string data designated by after the character string data designated by and stores the result into the area starting with the device number designated by (2) When character strings are linked, the "00 "...
Page 230: 16-Bit Bin Data Increment
INC, INCP, DEC, DECP 6.2.16 INC, INCP 16-bit BIN data increment 6.2.16 DEC, DECP 16-bit BIN data decrement INC, INCP, DEC, DECP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of INC/DEC. Command INC, DEC Command INCP, DECP : Head number of devices for INC (+1)/DEC (-1) operation (BIN 16 bits) Setting Internal Devices...
Page 231: 32-Bit Bin Data Increment
DINC, DINCP, DDEC, DDECP [List Mode] Device Step Instruction (2) The following is a down counter program. [Ladder Mode] Transfers 100 to D8 when X7 goes ON. In the state M38=OFF, decrement at D8 (D8 - 1) is executed when X8 goes from OFF to ON. At D8=0, M38 goes ON.
Page 232 DINC, DINCP, DDEC, DDECP DDEC (1) Subtracts -1 from the device designated by (32-bit data). b16 b15 b16 b15 73500 (BIN) 73499 (BIN) (2) When DDEC/DDECP operation is executed for the device designated by , whose content is 0, the value -1 is stored at the device designated by Operation Error (1) There is no operation error in the DINC(P) or DDEC(P) instruction.
Page 233: Data Conversion Instructions
BCD, BCDP, DBCD, DBCDP Data conversion instructions 6.3.1 BCD, BCDP Conversion from BIN data to BCD 4-digit data 6.3.1 DBCD, DBCDP Conversion from BIN data to BCD 8-digit data BCD, BCDP, DBCD, DBCDP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BCD/DBCD.
Page 234 BCD, BCDP, DBCD, DBCDP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The data of is other than 0 to 9999 when the BCD instruction is 4100...
Page 235: Conversion From Bcd 4-Digit Data To Bin Data
BIN, BINP, DBIN, DBINP 6.3.2 BIN, BINP Conversion from BCD 4-digit data to BIN data 6.3.2 DBIN, DBINP Conversion from BCD 8-digit data to BIN data BIN, BINP, DBIN, DBINP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BIN/DBIN.
Page 236 BIN, BINP, DBIN, DBINP Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 When values other than 0 to 9 are specified to any digits of The error above can be suppressed by turning ON SM722.
Page 237: (Single Precision)
FLT, FLTP, DFLT, DFLTP 6.3.3 FLT, FLTP Conversion from BIN 16-bit data to floating-point data (Single precision) DFLT, DFLTP Conversion from BIN 32-bit data to floating-point data (Single precision) Ver. High Basic Process LCPU Redundant Universal performance 6.3.3 FLT, FLTP, DFLT, DFLTP •...
Page 238 FLT, FLTP, DFLT, DFLTP (3) Due to the fact that 32-bit floating decimal point type real numbers are processed by simple 32-bit processing, the number of significant digits is 24 bits if the display is binary and approximately 7 digits if the display is decimal. For this reason, if the integer exceeds the range of -16777216 to 16777215 (24-bit BIN value), errors can be generated in the conversion value.
Page 239: (Double Precision)
FLTD, FLTDP, DFLTD, DFLTDP 6.3.4 FLTD, FLTDP Conversion from BIN 16-bit data to floating-point data (Double precision) DFLTD, DFLTDP Conversion from BIN 32-bit data to floating-point data (Double precision) 6.3.4 FLTD, FLTDP, DFLTD, DFLTDP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of FLTD/DFLTD.
Page 240: (Single Precision)
INT, INTP, DINT, DINTP [Operation] D3 D2 Conversion to real number 15923 15923 BIN value 64-bit floating-point real number (2) The following program converts the BIN 32-bit data at D20 and D21 to a 64-bit floating decimal point type real number, and stores the result at D0 to D3.
Page 241 INT, INTP, DINT, DINTP DINT (1) Converts 32-bit floating decimal point type real number designated by to BIN 32-bit data, and stores the result at the device number designated by Upper 16 bits Lower 16 bits BIN 32 bits 32-bit floating-point real number (2) The range of 32-bit floating decimal point type real numbers that can be designated at +1 or...
Page 242: (Double Precision)
INTD, INTDP, DINTD, DINTDP (2) The following program converts the 32-bit floating decimal point type real number at D20 and D21 to BIN 32-bit data and stores the result at D0 and D1. [Ladder Mode] [List Mode] Device Step Instruction [Operation] Integer conversion...
Page 243 INTD, INTDP, DINTD, DINTDP DINTD (1) Converts 64-bit floating decimal point type real number designated by to BIN 32-bit data, and stores the result at the device number designated by Upper 16 bits Lower 16 bits BIN 32 bit 64-bit floating-point real number (2) The range of 64-bit floating decimal point type real numbers that can be designated at +3, +2, +1 or...
Page 244: Conversion From Bin 16-Bit To Bin 32-Bit Data
DBL, DBLP [Operation] D23 D22 Conversion to integer 574968 574968.321 BIN value 64-bit floating-point real number D23 D22 Conversion to integer 2147483649.22 An operation erroe occurs because the specified data is larger than 2147483647. 64-bit floating-point real number 6.3.7 DBL, DBLP Conversion from BIN 16-bit to BIN 32-bit data 6.3.7 DBL, DBLP...
Page 245: Word, Wordp
WORD, WORDP 6.3.8 WORD, WORDP Conversion from BIN 32-bit to BIN 16-bit data 6.3.8 WORD, WORDP High Basic Process Redundant Universal LCPU performance Command WORD WORD Command WORDP WORDP : BIN 32-bit data or head number of the devices where the BIN 32-bit data is stored (BIN 32 bits) : Head number of the devices where the converted BIN 16-bit data will be stored (BIN 16 bits) Setting Internal Devices...
Page 246: Conversion From Bin 16-Bit Data To Gray Code
GRY, GRYP, DGRY, DGRYP 6.3.9 GRY, GRYP Conversion from BIN 16-bit data to Gray code 6.3.9 DGRY, DGRYP Conversion from BIN 32-bit data to Gray code GRY, GRYP, DGRY, DGRYP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of GRY, DGRY.
Page 247: Conversion From Gray Code To Bin 16-Bit Data
GBIN, GBINP, DGBIN, DGBINP Program Example (1) The following program converts the BIN data at D100 to Gray code when X10 is ON, and stores result at D200. [Ladder Mode] [List Mode] Device Step Instruction (2) The following program converts the BIN data at D10 and D11 to Gray code when X1C is ON, and stores it at D100 and D101.
Page 248: Complement Of 2 Of Bin 16-Bit Data (Sign Inversion)
NEG, NEGP, DNEG, DNEGP DGBIN Converts Gray code data at device designated by to BIN 32-bit data and stores at device designated by +1 (Upper 16 bits) (Lower 16 bits) Gray code 305419896 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 BIN 305419896 Operation Error...
Page 249 NEG, NEGP, DNEG, DNEGP Function (1) Reverses the sign of the 16-bit device designated by and stores at the device designated by 16 bit Before execution -21846 Sign conversion 21846 After execution (2) Used when reversing positive and negative signs. DNEG (1) Reverses the sign of the 32-bit device designated by and stores at the device designated by...
Page 250: Eneg, Enegp Floating-Point Sign Inversion (Single Precision)
ENEG, ENEGP 6.3.12 ENEG, ENEGP Floating-point sign inversion (Single precision) Ver. High Basic Process LCPU Redundant Universal performance 6.3.12 ENEG, ENEGP • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command ENEG ENEG Command ENEGP ENEGP : Head number of the devices where the 32-bit floating decimal point data whose sign is to be reversed is stored (real number) Internal Devices...
Page 251: Edneg, Ednegp Floating-Point Sign Inversion (Double Precision)
EDNEG, EDNEGP 6.3.13 EDNEG, EDNEGP Floating-point sign inversion (Double precision) 6.3.13 EDNEG, EDNEGP High Basic Process LCPU Redundant Universal performance Command EDNEG EDNEG Command EDNEGP EDNEGP : Head number of the devices where the 64-bit floating decimal point data whose sign is to be reversed is stored (real number) Setting Internal Devices R, ZR...
Page 252: Bkbcd, Bkbcdp
BKBCD, BKBCDP 6.3.14 BKBCD, BKBCDP Conversion from block BIN 16-bit data to BCD 4-digit data 6.3.14 BKBCD, BKBCDP High Basic Process Redundant Universal LCPU performance Command BKBCD BKBCD Command BKBCDP BKBCDP : Head number of the devices where BIN data is stored (BIN 16 bits) : Head number of the devices where the converted BCD data will be stored (BCD 4 digits) : Number of variable data blocks (BIN 16 bits) Setting...
Page 253: Bkbin, Bkbinp
BKBIN, BKBINP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The nth data from the device specified by is outside the 0 to 9999 4100 range.
Page 254 BKBIN, BKBINP Function (1) Converts BCD data (0 to 9999) n points from device designated by to BIN, and stores result following the device designated by BCD 1234 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 BCD 5678 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 BCD 1545...
Page 255: Econ, Econp
ECON, ECONP [Operation] D100 BCD 8080 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 D101 BCD 7654 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 D102 BCD 9999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 BIN conversion...
Page 256: Edcon, Edconp
EDCON, EDCONP Program Example (1) The program which converts 32-bit floating-point real number of the devices, D10 to D11, into 64-bit floating-point real number when X0 turns ON, and outputs the conversion result to the devices, D0 to D3. [Ladder Mode] [List Mode] Device Step...
Page 257 EDCON, EDCONP Program Example (1) The program which converts 64-bit floating-point real number of the devices, D10 to D13, into 32-bit floating-point real number when X0 turns ON, and outputs the conversion result to the devices, D0 to D1. [Ladder Mode] [List Mode] Instruction Device...
Page 258: Data Transfer Instructions
MOV, MOVP, DMOV, DMOVP Data Transfer Instructions 6.4.1 MOV, MOVP 16-bit data transfer 6.4.1 DMOV, DMOVP 32-bit data transfer MOV, MOVP, DMOV, DMOVP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of MOV/DMOV. Command MOV, DMOV Command MOVP, DMOVP : Data to be transferred or the number of the device where the data to be transferred is stored (BIN 16/32 bits) : Number of the device where the data will be transferred (BIN 16/32 bits)
Page 259: Emov, Emovp
EMOV, EMOVP (2) The following program stores the constant K155 at D8 when X8 goes ON. [Ladder Mode] [List Mode] Step Instruction Device 009B b8b7 1 0 0 1 1 0 1 1 (3) The following program stores the data from D0 and D1 at D7 and D8. [Ladder Mode] [List Mode] Instruction...
Page 260: Edmov, Edmovp
EDMOV, EDMOVP Program Example (1) The following program stores the real numbers at D10 and D11 at D0 and D1. [Ladder Mode] [List Mode] Step Instruction Device [Operation] 36.475 36.475 (2) The following program stores the real number -1.23 at D10 and D11 when X8 is ON. [Ladder Mode] [List Mode] Device...
Page 261: Mov, $Movp
$MOV, $MOVP Program Example (1) The following program stores the 64-bit floating decimal point type real number at D10 to D13 at D0 to D3. [Ladder Mode] [List Mode] Instruction Device Step [Operation] D13 D12 D3 D2 36.475 36.475 (2) The following program stores the real number -1.23 at D10 to D13 when X8 is ON. [Ladder Mode] [List Mode] Device...
Page 262 $MOV, $MOVP (2) Processing will be performed without error even in cases where the range for the devices storing the character data to be transferred ( +n) overlaps with the range of the devices which will store the character string data after it has been transferred ( +n).
Page 263: 16-Bit Data Negation Transfer
CML, CMLP, DCML, DCMLP 6.4.5 CML, CMLP 16-bit data negation transfer 6.4.5 DCML, DCMLP 32-bit data negation transfer CML, CMLP, DCML, DCMLP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of CML, DCML. Command CML, DCML Command CMLP, DCMLP : Data to be reversed or the number of the device where data to be reversed is stored (BIN 16/32 bits) : Number of the device where the reversing result will be stored (BIN 16/32 bits)
Page 264 CML, CMLP, DCML, DCMLP Program Example (1) The following program inverts the data from X0 to X7, and transfers result to D0. [Ladder Mode] [List Mode] Device Step Instruction [Operation] If "Number of bits of < Number of bits of "...
Page 265: Bmov, Bmovp
BMOV, BMOVP [Operation] If "Number of bits of < Number of bits of " X8 X7 These bits are all regarded as 0. 0 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 b28 b27 1 0 1 1 1 0 0 0 1 1 0 1 0 0 1 1 D0, 1...
Page 266 BMOV, BMOVP Function (1) Transfers in batch 16-bit data of n points from the device designated by to location n points from the device designated by 1234 1234 Block 5678 5678 transfer 7FF0 7FF0 +(n-2) 6FFF +(n-2) 6FFF +(n-1) 553F 553F +(n-1) (2) Transfers can be accomplished even in cases where there is an overlap between the source and destination device.
Page 267 BMOV, BMOVP (6) Selection whether to check a device range Whether to check a device range during execution of the BMOV instruction can be selected with the device range check inhibit flag (SM237) (only when the conditions for subset processing are established). While SM237 is ON, whether + (n) -1 and + (n) - 1 are within the device range or not are not checked.
Page 268: Fmov, Fmovp
FMOV, FMOVP (2) The following program outputs the data at X20 to X2F to D100 to D103 in 4-point units. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Before execution 0 1 1 1 0 1 1 0 0 1 0 0 After execution (destination of transfer) 0 0 0 0 0 0 0 0...
Page 269 FMOV, FMOVP (4) Selection whether to check a device range Whether to check a device range during execution of the FMOV instruction can be selected with the device range check inhibit flag (SM237) (only when the conditions for subset processing are established). While SM237 is ON, whether + (n) - 1 is within the device range or not is not checked.
Page 270: Dfmov, Dfmovp
DFMOV, DFMOVP [Operation] Before execution 0 1 1 1 0 0 1 0 1 1 1 0 Ignored After execution (destination of transfer) 0 0 0 0 0 0 0 0 1 1 1 0 D100 0 0 0 0 0 0 0 0 1 1 1 0 D101...
Page 271 DFMOV, DFMOVP (2) If specifies data of a device with digit specification, the amount of data to be transferred will be the amount of the data specified digit. If K5Y0 is specified by , the lower 20 bits (five digits) of the word device specified by will be the object.
Page 272: 16-Bit Data Exchanges
XCH, XCHP, DXCH, DXCHP [Operation] Y14 Y13 Ignored 20 bits (five digits) data b20 b19 D11,D10 D13,D12 Transfer D15,D14 D17,D16 20 bits (five digits) Filled with 0s 6.4.9 XCH, XCHP 16-bit data exchanges 6.4.9 DXCH, DXCHP 32-bit data exchanges XCH, XCHP, DXCH, DXCHP High Basic Process...
Page 273: Bxch, Bxchp
BXCH, BXCHP Operation Error (1) There is no error in the XCH (P) or DXCH (P) instruction. Program Example (1) The following program exchanges the present value of T0 with the contents of D0 when X8 goes ON. [Ladder Mode] [List Mode] Device Step...
Page 274 BXCH, BXCHP Function (1) Exchanges 16-bit data of n points from device designated by and 16-bit data of n points from device designated by 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1...
Page 275: Swap, Swapp
SWAP, SWAPP 6.4.11 SWAP, SWAPP Upper and lower byte exchanges 6.4.11 SWAP, SWAPP High Basic Process LCPU Redundant Universal performance Command SWAP SWAP Command SWAPP SWAPP : Head number of the devices where the data is stored (BIN 16 bits) Setting Internal Devices R, ZR...
Page 276: Program Branch Instructions
CJ, SCJ, JMP Program Branch Instructions 6.5.1 CJ, SCJ, JMP Pointer branch 6.5.1 CJ, SCJ, JMP High Basic Process LCPU Redundant Universal performance Command Command Label Command : Pointer number of jump destination (Device name) Setting Internal Devices R, ZR Constants Other Data...
Page 277 CJ, SCJ, JMP (1) Unconditionally executes program of designated pointer number within the same program file. Note the following points when using the jump instruction. 1. After the timer coil has gone ON, accurate measurements cannot be made if there is an attempt to jump the timer of a coil that has been turned ON using the CJ, SCJ or JMP instructions.
Page 278 CJ, SCJ, JMP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified pointer number is not set before the END instruction. A 4210 pointer number which is not in use as a label in the same program has been specified.
Page 279: Jump To End
GOEND 6.5.2 GOEND Jump to END 6.5.2 GOEND High Basic Process LCPU Redundant Universal performance Command GOEND GOEND Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Jumps to the FEND or END instruction in the same program file. Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 280: Program Execution Control Instructions
DI, EI, IMASK Program Execution Control Instructions 6.6.1 Interrupt disable Interrupt enable 6.6.1 IMASK Interrupt program mask DI, EI, IMASK High Basic Process Redundant Universal LCPU performance When the Basic model QCPU is used Sequence program IMASK IMASK : Interrupt mask data or head number of the devices where the interrupt mask data is stored (BIN 16 bits) Setting Internal Devices R, ZR...
Page 281 DI, EI, IMASK IMASK (1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 8 points from the device designated by • 1(ON)..Interrupt program execution enabled • 0(OFF)..Interrupt program execution disabled (2) The interrupt pointer numbers corresponding to the individual bits are as shown below: b14 b13 b12 b11 b10 b9 I15 I14...
Page 282 DI, EI, IMASK Program Example (1) The following program is designed to enable the execution of only the interrupt programs having the interrupt pointer numbers I1 and I3 while X0 is ON. [Ladder Mode] [List Mode] Device Step Instruction When the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU or LCPU is used Sequence program IMASK IMASK...
Page 283 DI, EI, IMASK The EI instruction is used to clear the interrupt disable state resulting from the execution of the DI instruction, and to create a state in which the interrupt program designated by the interrupt pointer number enabled by the IMASK instruction and the fixed cycle execution type program can be executed.
Page 284 DI, EI, IMASK 1. An interrupt pointer occupies 1 step. Stored at step 50 IRET 2. For the information on interrupt conditions, link direct devices, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals) 3.
Page 285 DI, EI, IMASK Program Example (1) The following program creates an execution enabled state for the interrupt program marked by the interrupt pointer number when X0 is ON. [Ladder Mode] [List Mode] Instruction Device Step...
Page 286: Recovery From Interrupt Programs
IRET 6.6.2 IRET Recovery from interrupt programs 6.6.2 IRET High Basic Process LCPU Redundant Universal performance IRET IRET Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Indicates the completion of interrupt program processing. (2) Returns to sequence program processing following the execution of the IRET instruction. Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 287: I/O Refresh Instructions
RFS, RFSP I/O Refresh Instructions 6.7.1 RFS, RFSP I/O refresh 6.7.1 RFS, RFSP High Basic Process LCPU Redundant Universal performance Command Command RFSP RFSP : Head number of the devices to be refreshed (bits) : Number of refreshes (BIN 16 bits) Setting Internal Devices Constants...
Page 288 RFS, RFSP Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4101 The points specified in n exceed those of the proximate I/O. ––...
Page 289: Other Convenient Instructions
UDCNT1 Other Convenient Instructions 6.8.1 UDCNT1 Counter 1-phase input up or down 6.8.1 High Basic Process LCPU Redundant Universal performance UDCNT1 Command UDCNT1 UDCNT1 + 0: Input number for count input (bits) + 1: For setting count up/down (bits) • OFF: Count up (add numbers when counting) •...
Page 290 UDCNT1 1. With the UDCNT1 instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be counted must have longer ON and OFF times than the interrupt interval of the CPU module.
Page 291: Udcnt2
UDCNT2 6.8.2 UDCNT2 Counter 2-phase input up or down 6.8.2 UDCNT2 High Basic Process LCPU Redundant Universal performance Command UDCNT2 UDCNT2 + 0: Input number for count input (A phase pulse) (bits) + 1: Input number for count input (B phase pulse) (bits) : Number of the counter to be enabled to start counting with the UDCNT2 instruction (Device name) : Value to set (BIN 16 bits) Setting...
Page 292 UDCNT2 1. With the UDCNT2 instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be counted must have longer ON and OFF times than the interrupt interval of the CPU module.
Page 293: Ttmr
TTMR 6.8.3 TTMR Teaching timer 6.8.3 TTMR High Basic Process LCPU Redundant Universal performance Command TTMR TTMR + 0: The device where measurement value is stored (BIN 16 bit) + 1: For CPU module system use (BIN 16 bit) : Measurement value multiplier (BIN 16 bits) Setting Internal Devices Constants...
Page 294: Stmr
STMR Program Example (1) The following program stores the amount of time that X0 is ON at D0. [Ladder Mode] [List Mode] Instruction Device Step 6.8.4 STMR Special function timer 6.8.4 STMR High Basic Process Redundant Universal LCPU performance Command STMR STMR : Timer number (word)
Page 295 STMR (3) The timer contact goes ON at the leading edge of the command for the STMR instruction, and after the trailing edge is reached, the timer coil goes OFF at the trailing edge of the STMR instruction command. The timer contact is used by the CPU module system, and cannot be used by the user. Command for STMR instruction (Coil)
Page 296: Rotc
ROTC Program Example (1) The following program turns Y0 and Y1 ON and OFF once each second (flicker) when X20 is ON. (Uses 100 ms timer) [Ladder Mode] [List Mode] Step Instruction Device [Timing Chart] M1, Y0 M2, Y1 1 sec 1 sec 6.8.5 ROTC...
Page 297 ROTC Function (1) This control functions to enable shortest direction control of the rotary table to the position of the station number designated by +1 in order to remove or deposit an item whose number has been designated by +2 on a rotary table with equal divisions of the value designated by n1.
Page 298: Ramp
RAMP Program Example (1) The following program deposits the item at section D2 on a 10-division rotary table at the station at section D1, and the two sections ahead and behind this determine the rotation direction and control speed of the motor when the table is being rotated at low speed.
Page 299 RAMP Function (1) When the execution command is ON, the following processing is executed. • Shifts from the value specified by n1 to the value specified by n2 in the number of times specified by n3. • For n3, designate the number of scans (number of shifts) required for shift from n1 to n2. No operation if other than 0<n3<32768.
Page 300: Spd
Program Example (1) The following program changes the contents of D0 from 10 to 100 in a total of 6 scans, and saves the contents of D0 when the move has been completed. [Ladder Mode] [List Mode] Device Step Instruction [Timing Chart] 1scan 1scan...
Page 301 Function (1) The number of turning OFF ON input of the device specified by is counted for just the amount of time specified by n, and the count results are stored in the device specified by Start of measurement n [ms] n [ms] Execution command Measurement result is stored at (D)
Page 302: Plsy
PLSY 6.8.8 PLSY Fixed cycle pulse output 6.8.8 PLSY High Basic Process LCPU Redundant Universal performance Command PLSY PLSY : Frequency or the number of the device where frequency is stored (BIN 16 bits) : Outputs count or the number of the device where the outputs count is stored (BIN 16 bits) : Number of the device to which pulses are output (bits) Setting Internal Devices...
Page 303: Pwm
Program Example (1) The following program outputs a 10 Hz pulse 5 times to Y20 when X0 is ON. [Ladder Mode] [List Mode] Instruction Device Step 6.8.9 Pulse width modulation 6.8.9 High Basic Process Redundant Universal LCPU performance Command : ON time or the number of the device where the ON time is stored (BIN 16 bits) : Frequency or the number of the device where the frequency is stored (BIN 16 bits) : Number of the device to which pulses are output (bits) Internal Devices...
Page 304: Mtr
1. With the PWM instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.) The interrupt interval of individual modules is shown below: CPU Module Type Name...
Page 305 Function (1) It reads the input from 16 points n-rows starting from the input number designated by , then stores fetched input data from the device designated by onward. (2) One row (16 points) can be fetched in 1 scan. (3) Fetching from the first to the n th row is repeated.
Page 306 [Operation] 3rd row X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F 2nd row X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F 1st row X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F...
Page 307: Chapter 7 Application Instructions
CHAPTER 7 APPLICATION INSTRUCTIONS Logical operation instructions (1) The logical operation instructions perform logical sum, logical product or other logical operations in 1-bit units. Example Category Processing Details Formula for Operation Logical product Becomes 1 only when both input A and A ·...
Page 308: Logical Products With 16-Bit Data
WAND, WANDP, DAND, DANDP 7.1.1 WAND, WANDP Logical products with 16-bit data 7.1.1 DAND, DANDP Logical products with 32-bit data WAND, WANDP, DAND, DANDP High Basic Process Redundant Universal LCPU performance When two data are set ( indicates an instruction symbol of WAND/DAND. Command WAND,DAND Command...
Page 309: Wand, Wandp
WAND, WANDP, DAND, DANDP Program Example (1) The following program masks the digit in the 10s place of the 4-digit BCD value at D10 (second digit from the end) to 0 when XA is turned ON. [Ladder Mode] [List Mode] Step Instruction Device...
Page 310 WAND, WANDP, DAND, DANDP WAND (1) A logical product operation is conducted for each bit of the 16-bit data of the device designated at and the 16-bit data of the device designated at , and the results are stored in the device designated at (2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0"...
Page 311 WAND, WANDP, DAND, DANDP (2) The following program performs a logical product operation on the data at D10 and at D20 when X1C is ON, and stores the results from M0 to M11. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Not changed (3) The following program masks the digit in the hundred-thousands place of the 8-digit BCD value at D10 and D11 (sixth...
Page 312: Bkand, Bkandp
BKAND, BKANDP 7.1.2 BKAND, BKANDP Block logical products 7.1.2 BKAND, BKANDP High Basic Process LCPU Redundant Universal performance Command BKAND BKAND Command BKANDP BKANDP *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) *1 : Head number of the devices where the operation result will be stored (BIN 16 bits) : Number of operation data blocks (BIN 16 bits)
Page 313 BKAND, BKANDP (2) The constant designated by can be between -32768 and 32767 (BIN 16-bit data). 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b8b7 BKAND...
Page 314: Logical Sums Of 16-Bit Data
WOR, WORP, DOR, DORP 7.1.3 WOR, WORP Logical sums of 16-bit data 7.1.3 DOR, DORP Logical sums of 32-bit data WOR, WORP, DOR, DORP High Basic Process Redundant Universal LCPU performance When two data are set ( , ( +1, ( +1, ( +1, indicates an instruction symbol of WOR/DOR.
Page 315: Wor, Worp
WOR, WORP, DOR, DORP Program Example (1) The following program performs a logical sum operation on the data at D10 and D20 when XA is turned ON, and stores the results at D10. [Ladder Mode] [List Mode] Device Step Instruction [Operation] (2) The following program performs a logical sum operation on the 32-bit data from X0 to X1F, and on the hexadecimal value FF00FF00...
Page 316 WOR, WORP, DOR, DORP When three data are set ( , ( +1, ( +1, ( +1, indicates an instruction symbol of WOR/DOR. Command WOR, DOR Command WORP, DORP : Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits) S1 S2 : Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits) Setting...
Page 317 WOR, WORP, DOR, DORP Program Example (1) The following program performs a logical sum operation on the data from X10 to X1B, and the data at D33, and stores the result at Y30 to Y3B when XA is ON. [Ladder Mode] [List Mode] Step Instruction...
Page 318: Bkor, Bkorp
BKOR, BKORP 7.1.4 BKOR, BKORP Block logical sum operations 7.1.4 BKOR, BKORP High Basic Process Redundant Universal LCPU performance Command BKOR BKOR Command BKORP BKORP *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) *1 : Head number of the devices where the operation result will be stored (BIN 16 bits) : Number of operation data blocks (BIN 16 bits)
Page 319 BKOR, BKORP (2) The constant designated by can be between -32768 and 32767 (BIN 16-bit data). 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1...
Page 320: 16-Bit Exclusive Or Operations
WXOR, WXORP, DXOR, DXORP 7.1.5 WXOR, WXORP 16-bit exclusive OR operations 7.1.5 DXOR, DXORP 32-bit exclusive OR operations WXOR, WXORP, DXOR, DXORP High Basic Process Redundant Universal LCPU performance When two data are set , ( +1, ( +1, ( +1, indicates an instruction symbol of WXOR/DXOR.
Page 321: Wxor, Wxorp
WXOR, WXORP, DXOR, DXORP Program Example (1) The following program performs an exclusive OR operation on the data at D10 and D20 when XA is ON, and stores the result at D10. [Ladder Mode] [List Mode] Step Instruction Device [Operation] (2) The following program compares the bit pattern of the 32-bit data from X20 to X3F with the bit pattern of the data at D9 and D10 when X6 is ON, and stores the number of differing bits at D16.
Page 322 WXOR, WXORP, DXOR, DXORP When three data are set ( +1, ( +1, ( +1, indicates an instruction symbol of WXOR/DXOR. Command WXOR, DXOR Command WXORP, DXORP : Data for an exclusive OR operation or head number of the devices where the data is stored (BIN 16/32 bits) S1 S2 : Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits) Internal Devices...
Page 323 WXOR, WXORP, DXOR, DXORP Program Example (1) The following program conducts an exclusive OR operation on the data from X10 to X1B and the data at D33 when X10 is ON, and outputs the result to Y30 to Y3B. [Ladder Mode] [List Mode] Step Instruction...
Page 324: Bkxor, Bkxorp
BKXOR, BKXORP 7.1.6 BKXOR, BKXORP Block exclusive OR operations 7.1.6 BKXOR, BKXORP High Basic Process Redundant Universal LCPU performance Command BKXOR BKXOR Command BKXORP BKXORP *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) *1 : Head number of the devices where the operation result will be stored (BIN 16 bits) : Number of operation data blocks (BIN 16 bits)
Page 325 BKXOR, BKXORP (2) The constant designated by can be between -32768 and 32767 (BIN 16-bit data). 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 +(n 2)
Page 326: 16-Bit Data Exclusive Nor Operations
WXNR, WXNRP, DXNR, DXNRP [Operation] D100 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D101 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D102 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D200...
Page 327 WXNR, WXNRP, DXNR, DXNRP DXNR (1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by and the 32-bit data of the device designated by , and stores the results at the device designated by (2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation. Operation Error (1) There is no operation error in the WXNR(P) or DXNR(P) instruction.
Page 328 WXNR, WXNRP, DXNR, DXNRP [Operation] X3C X3B X38 X37 X34 X33 X2C X2B X28 X27 X24 X23 X3F to X20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D17,D16 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 1 D17,D16 0...
Page 329: Wxnr, Wxnrp
WXNR, WXNRP, DXNR, DXNRP DXNR (1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by and the 32-bit data of the device designated by , and stores the results at the device designated by (2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation. Operation Error There is no operation error in the WXNR(P) or DXNR(P) instruction.
Page 330: Bkxnr, Bkxnrp
BKXNR, BKXNRP [Operation] D21,D20 D11,D10 D41,D40 7.1.8 BKXNR, BKXNRP Block exclusive NOR operations 7.1.8 BKXNR, BKXNRP High Basic Process LCPU Redundant Universal performance Command BKXNR BKXNR Command BKXNRP BKXNRP *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) *1 : Head number of the devices where the operation result will be stored (BIN 16 bits) : Number of operation data blocks (BIN 16 bits)
Page 331 BKXNR, BKXNRP (2) The constant designated by can be between -32768 and 32767 (BIN 16-bit data). 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 b8b7 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0...
Page 332: Rotation Instruction
ROR, RORP, RCR, RCRP Rotation instruction 7.2.1 ROR, RORP, RCR, RCRPRight rotation of 16-bit data 7.2.1 ROR, RORP, RCR, RCRP High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of ROR/RCR. Command ROR, RCR Command RORP, RCRP : Head number of the devices to rotate (BIN 16 bits) : Number of rotations (0 to 15) (BIN 16 bits) Internal Devices Setting...
Page 333 ROR, RORP, RCR, RCRP (1) Rotates 16-bit data of the device designated by , including the carry flag, n-bits to the right. The carry flag is ON or OFF depending on the status prior to the execution of the ROR instruction. Carry flag (SM700) b14 b13 b12 b11 b10 b9...
Page 334 ROR, RORP, RCR, RCRP (2) The following program rotates the contents of D0, including the carry flag, 3 bits to the right when XC is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Carry flag (SM700) b14 b13 b12 b11b10 b9 b6 b5 b4 b3 b2 b1 Carry flag (SM700)
Page 335: Rol, Rolp, Rcl, Rclp Left Rotation Of 16-Bit Data
ROL, ROLP, RCL, RCLP 7.2.2 ROL, ROLP, RCL, RCLPLeft rotation of 16-bit data 7.2.2 ROL, ROLP, RCL, RCLP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ROL/RCL. Command ROL, RCL Command ROLP, RCLP : Head number of the devices to rotate (BIN 16 bits) : Number of rotations (0 to 15) (BIN 32 bits) Internal Devices Setting...
Page 336 ROL, ROLP, RCL, RCLP (1) Rotates the 16-bit data of the device designated by , including the carry flag, n-bits to the left. The carry flag turns ON or OFF depending on its status prior to the execution of RCL instruction. Carry flag b14 b13 b12 b11 b8 b7 b6 b5 b4 b3 b2 b1 b0...
Page 337: Dror, Drorp, Drcr, Right Rotation Of 32-Bit Data
DROR, DRORP, DRCR, DRCRP (2) The following program rotates the contents of D0, including the carry flag, 3 bits to the left when XC is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Carry flag (SM700) b14 b13 b12 b11b10 b9 b6 b5 b4 b3 b2 b1 Carry flag (SM700)
Page 338 DROR, DRORP, DRCR, DRCRP DRCR (1) Rotates 32-bit data, including carry flag, at device designated by n bits to the right. The carry flag goes ON or OFF depending on its status prior to the execution of the DRCR instruction. Carry flag b30 b29 b28 b27 b15b14...
Page 339: Drol, Drolp, Drcl
DROL, DROLP, DRCL, DRCLP 7.2.4 DROL, DROLP, DRCL, Left rotation of 32-bit data 7.2.4 DRCLP DROL, DROLP, DRCL, DRCLP High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of DROL/DRCL. Command DROL, DRCL Command DROLP, DRCLP : Head number of the devices to rotate (BIN 32 bits) : Number of rotations (0 to 31) (BIN 16 bits) Internal Devices Setting...
Page 340 DROL, DROLP, DRCL, DRCLP Operation Error (1) There is no operation error in the DROL(P) or DRCL(P) instruction. Program Example (1) The following program rotates the contents of D0 and D1, not including the carry flag, 4 bits to the left when XC is ON. [Ladder Mode] [List Mode] Step...
Page 341: Shift Instruction
SFR, SFRP, SFL, SFLP Shift instruction 7.3.1 SFR, SFRP n-bit shift to right of 16-bit data 7.3.1 SFL, SFLP n-bit shift to left of 16-bit data SFR, SFRP, SFL, SFLP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of SFR/SFL. Command SFR, SFL Command...
Page 342 SFR, SFRP, SFL, SFLP (1) Shifts 16-bit data at device designated by n bits to the left. Bits starting from the lowest bit to n bit are filled with 0s. b14 b13 b12 b11b10 b9 b6 b5 b4 b3 b2 b1 When n=8: Carry flag (SM700)
Page 343: Bsfr, Bsfrp
BSFR, BSFRP, BSFL, BSFLP [Operation] Carry flag (SM700) X14 X13 Filled with 0s. 7.3.2 BSFR, BSFRP 1-bit shift to right of n-bit data 7.3.2 BSFL, BSFLP 1-bit shift to left of n-bit data BSFR, BSFRP, BSFL, BSFLP High Basic Process LCPU Redundant Universal performance...
Page 344 BSFR, BSFRP, BSFL, BSFLP Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The points specified in n exceed those of the corresponding device 4101 specified in Program Example...
Page 345: Sftbr, Sftbrp
SFTBR, SFTBRP, SFTBL, SFTBLP 7.3.3 SFTBR, SFTBRP n-bit shift to right of n-bit data SFTBL, SFTBLP n-bit shift to left of n-bit data Ver. High Basic Process LCPU Redundant Universal performance 7.3.3 SFTBR, SFTBRP, SFTBL, SFTBLP • QnU(D)(H)CPU, QnUDE(H)CPU: The serial number (first five digits) is "10102"...
Page 346 SFTBR, SFTBRP, SFTBL, SFTBLP (2) n1 and n2 are specified under the condition that n1 is larger than n2. If the value of n2 is equal to or larger than the value of n1, the remainder of n2 / n1 (n2 devided by n1) is used for a shift. However, if the remainder of n2 / n1 is 0, the instruction will be not processed.
Page 347: Dsfr, Dsfrp
DSFR, DSFRP, DSFL, DSFLP 7.3.4 DSFR, DSFRP 1-word shift to right of n-word data 7.3.4 DSFL, DSFLP 1-word shift to left of n-word data DSFR, DSFRP, DSFL, DSFLP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DSFR/DSFL. Command DSFR, DSFL Command...
Page 348: Sftwr, Sftwrp
SFTWR, SFTWRP, SFTWL, SFTWLP Program Example (1) The following program shifts the contents of D683 to D689 to the right when XB is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Designation range for the DSFRP instruction D689 D688 D687 D686...
Page 349 SFTWR, SFTWRP, SFTWL, SFTWLP Function SFTWR(P) (1) This instruction shifts n1 words data in the devices starting from the device specified by to the right by n2 words. n1=9, n2=4 Filled with 0 (2) The n2 words data in the devices starting from the highest device are filled with 0s. (3) If the value specified by n1 or n2 is 0, the instruction will be not processed.
Page 350 SFTWR, SFTWRP, SFTWL, SFTWLP Program Example (1) The following program shifts the 8 words (n1) data stored in the devices starting from D10 specified by to the right by 2 words (n2), when M0 is turned on. [Ladder Mode] [List Mode] Instruction Device Step...
Page 351: Bit Processing Instructions
BSET, BSETP, BRST, BRSTP Bit processing instructions 7.4.1 BSET, BSETP Bit set for word devices 7.4.1 BRST, BRSTP Bit reset for word devices BSET, BSETP, BRST, BRSTP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BSET/BRST. Command BSET, BRST Command...
Page 352: Test, Testp, Dtest
TEST, TESTP, DTEST, DTESTP Program Example (1) The following program resets the 8th bit of D8 (b8) to 0 when XB is OFF, and sets the 3rd bit of D8 (b3) to 1 when XB is [Ladder Mode] Resets b8 of D8. Sets b3 of D8.
Page 353 TEST, TESTP, DTEST, DTESTP Function TEST (1) Fetches bit data at the location designated by within the word device designated by , and writes it to the bit device designated by (2) The bit device designated by is OFF when the relevant bit is "0" and ON when it is "1". (3) The position designated by indicates the position of an individual bit in a 1-word data block (0 to 15).
Page 354: Bkrst, Bkrstp
BKRST, BKRSTP (2) The following program turns Y40 ON or OFF, depending on the status of the 19th bit of the 2-word data (W0 and W1). [Ladder Mode] [List Mode] Step Instruction Device [Operation] 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 0 Turns Y40 OFF since b19 is "0."...
Page 355 BKRST, BKRSTP Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The points specified in n exceed those of the corresponding device 4101 specified in Program Example...
Page 356: Data Processing Instructions
SER, SERP, DSER, DSERP Data processing instructions 7.5.1 SER, SERP 16-bit data search 7.5.1 DSER, DSERP 32-bit data search SER, SERP, DSER, DSERP High Basic Process Redundant Universal LCPU performance Command SER, DSER Command SERP, DSERP : Search data or head number of the devices where the search data is stored (BIN 16/32 bits) : Data to be searched or head number of the devices where the data to be searched is stored (BIN 16 bits) : Head number of the devices where the search result will be stored (BIN 16 bits) : Number of searches (BIN 16 bits)
Page 357 SER, SERP, DSER, DSERP DSER (1) Searches n points from the device designated by in 32-bit units (2 n points in 16-bit units) regarding 32-bit data of the device designated by +1 and as a keyword. Then, the number of matches with the keyword is stored at the device designated by +1, and the first matched device number (in the relative number from ) is stored at the device...
Page 358: 16-Bit Data Check
SUM, SUMP, DSUM, DSUMP Program Example (1) The following program searches D100 to D105 for the contents of D0 when X20 is ON, and stores the search results at W0 and W1. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Search data Data to be searched D100...
Page 359 SUM, SUMP, DSUM, DSUMP Function From the 16-bit data in the device designated by , stores the total number of bits where 1 is set, in the device designated by 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 1 Total number of bits where 1 is set 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Stores the total number of bits where 1 is set in BIN.
Page 360: Deco, Decop
DECO, DECOP [Operation] 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 D100, D101 Stores the total number of bits where 1 is set into D0. 7.5.3 DECO, DECOP Decoding from 8 to 256 bits...
Page 361: Enco, Encop
ENCO, ENCOP Program Example (1) The following program decodes the 3 bits from X0 and stores the results at M10 when X20 is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] When 6 is designated at X0 to X2 Decoding result If 3 bits are designated as significant bits, 8 points are occupied.
Page 362: 7-Segment Decode
SEG, SEGP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The vaue of n is other than 0 to 8. 4100 All data 2 bits from...
Page 363 SEG, SEGP (2) If is a bit device, indicates the head number of the devices storing the 7-segment display data; if it is a word device, indicates the number of the device storing the data. Before execution After execution Bit device SEG K7 K2Y48 0 0 1 0 0 1 1 1 8 points...
Page 364: 4-Bit Dissociation Of 16-Bit Data
DIS, DISP Program Example (1) The following program converts the data from XC to XF to 7-segment display data and outputs it to Y38 to Y3F when X0 is turned ON. [Ladder Mode] [List Mode] Device Step Instruction [Timing Chart] Y38 to Y3F *1: The data Y38 to Y3F will not change until the next data is output.
Page 365: 4-Bit Linking Of 16-Bit Data
UNI, UNIP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 The value of n is other than 0 to 4. The range n-points from exceeds the range of the corresponding 4101...
Page 366 UNI, UNIP Function (1) Links lower 4 bits of 16-bit data n-points from device designated by to 16-bit device designated by b11 b8 Ignored Linked data (2) The bits of the upper (4-n) digits of the device designated by become 0. (3) The value of n can be designated at between 1 and 4.
Page 367: Dissociation Of Random Data
NDIS, NDISP, NUNI, NUNIP 7.5.8 NDIS, NDISP Dissociation of random data 7.5.8 NUNI, NUNIP Linking of random data NDIS, NDISP, NUNI, NUNIP High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of NDIS/NUNI. Command NDIS, NUNI Command NDISP, NUNIP Head number of the devices where data to be dissociated/linked is stored (BIN 16 bits) Head number of the devices where the dissociated/linked data will be stored (BIN 16 bits) Head number of the devices where the units of dissociation/linking will be stored (BIN 16 bits)
Page 368 NDIS, NDISP, NUNI, NUNIP NUNI (1) Links individual bits of data stored into the area starting from the device number designated by in the number of bits specified by , and stores them following the device number designated by Designation of the number of linked bits Designation of the end of setting b15b14b13 Number of bits...
Page 369 NDIS, NDISP, NUNI, NUNIP Program Example (1) The following program dissociates data of 4, 3, and 6 bits respectively from the lower bits of D0, and stores them from D10 to D12. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b4b3 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 4 bits...
Page 370: Wtob, Wtobp Data Dissociation In Byte Units
WTOB, WTOBP, BTOW, BTOWP [Operation] 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 4 bits b2 b0 0 1 0 1 1 1 1 0 1 0 0 0 1 1 0 1 3 bits 0 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0 6 bits...
Page 371 WTOB, WTOBP, BTOW, BTOWP (2) Setting the number of bytes with n automatically determines the range of the 16-bit data designated by and the range of the devices to store the byte data designated by (3) No processing will be conducted when the number of bytes designated by n is "0". (4) The "00 "...
Page 372 WTOB, WTOBP, BTOW, BTOWP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The range of the values in n exceeds that of the device specified by 4101 The range of the values in n exceeds that of the device specified by...
Page 373: Maximum Value Search For 16-Bit Data
MAX, MAXP, DMAX, DMAXP 7.5.10 MAX, MAXP Maximum value search for 16-bit data 7.5.10 DMAX, DMAXP Maximum value search for 32-bit data MAX, MAXP, DMAX, DMAXP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of MAX/DMAX. Command MAX, DMAX Command MAXP ,DMAXP...
Page 374 MAX, MAXP, DMAX, DMAXP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The points specified in n exceed those of the corresponding device 4101 specified in...
Page 375: Minimum Value Search For 16-Bit Data
MIN, MINP, DMIN, DMINP 7.5.11 MIN, MINP Minimum value search for 16-bit data 7.5.11 DMIN, DMINP Minimum value search for 32-bit data MIN, MINP, DMIN, DMINP High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of MIN/DMIN. Command MIN, DMIN Command MINP, DMINP...
Page 376 MIN, MINP, DMIN, DMINP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The points specified in n exceed those of the corresponding device 4101 ––...
Page 377: Bin 16 Bit-Data Sort Operations
SORT, DSORT 7.5.12 SORT BIN 16 bit-data sort operations 7.5.12 DSORT BIN 32 bit-data sort operations SORT, DSORT High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of SORT/DSORT. Command SORT, DSORT : Head device number in the table to be sorted (BIN 16/32 bits) : Number of data blocks to be sorted (BIN 16 bits) : Number of data blocks to be compared in one sort operation (BIN 16 bits) : Number of the bit device to be turned ON at the completion of the sort operation (bits)
Page 378 SORT, DSORT (5) The 2 points from the device designated by are used by the system during the execution of the SORT instruction. These 2 points from the device designated by should therefore not be used by the user. Changing these points may cause an error code to be returned (Error code: 4100). (6) If the value of n is changed during the execution of the SORT instruction, the sort will be conducted in accordance with the number of sort data blocks after the change.
Page 379 SORT, DSORT Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 is 0 or a negative value. The range from S1 to (S1 + n/2 n) (including S1) overlaps the range 4101...
Page 380: Wsum, Wsump
WSUM, WSUMP [Operation] Data after sort D1, D0 -99999 D3, D2 -1111 Data before sort D5, D4 D1, D0 456789 5000 D7, D6 D3, D2 -1111 D9, D8 456789 D5, D4 5000 D1, D0 D7, D6 456789 D9, D8 -99999 D3, D2 5000 D5, D4...
Page 381: Dwsum, Dwsump
DWSUM, DWSUMP Program Example (1) The following program adds the 16-bit BIN data from D10 to D14, and stores it in D100 and D101 when X1C is turned [Ladder Mode] [List Mode] Step Instruction Device [Operation] 4500 (BIN) 2500 (BIN) 3276 (BIN) 14948 (BIN) D101,D100...
Page 382 DWSUM, DWSUMP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The points specified in n exceed those of the corresponding device 4101 specified in The device specified in...
Page 383: Mean, Meanp Calculation Of Averages For 16-Bit Data
MEAN, MEANP, DMEAN, DMEANP 7.5.15 MEAN, MEANP Calculation of averages for 16-bit data DMEAN, DMEANP Calculation of averages for 32-bit data Ver. High Basic Process LCPU Redundant Universal 7.5.15 performance MEAN, MEANP, DMEAN, DMEANP • QnU(D)(H)CPU, QnUDE(H)CPU: The serial number (first five digits) is "10102"...
Page 384 MEAN, MEANP, DMEAN, DMEANP Program Example (1) The following program stores the average value of 16-bit data stored from D0 to D2 into D10, when M0 is turned on. [Ladder Mode] [List Mode] Step Instruction Device [Operation] (BIN) (BIN) (BIN) (BIN) (2) The following program stores the average value of 32-bit data stored from D0 to D5 into D10 and D11, when M0 is turned [Ladder Mode]...
Page 385: Structure Creation Instructions
FOR, NEXT Structure creation instructions 7.6.1 FOR, NEXT FOR to NEXT instruction loop 7.6.1 FOR, NEXT High Basic Process LCPU Redundant Universal performance Repeat program NEXT NEXT : Number of repetitions of FOR to NEXT loop (1 to 32767) (BIN 16 bits) Internal Devices Setting Constants...
Page 386 FOR, NEXT Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code After the FOR instruction was executed, the END, FEND, or GOEND instruction was executed prior to the NEXT instruction.
Page 387: Break, Breakp
BREAK, BREAKP 7.6.2 BREAK, BREAKP Forced end of FOR to NEXT instruction loop 7.6.2 BREAK, BREAKP High Basic Process LCPU Redundant Universal performance Command BREAK BREAK Command BREAKP BREAKP : Number of the device where the remaining number of loops will be stored (BIN 16 bits) : Number of the pointer (device name (pointer)) where the program is branched at the forced end of a loop.
Page 388: Subroutine Program Calls
CALL, CALLP Program Example (1) The following program forces the FOR to NEXT loop to end when the value of D0 reaches 30 (when the FOR to NEXT loop has been executed 30 times). [Ladder Mode] [List Mode] Step Instruction Device Remark The value 71 is stored at D1 when the BREAK instruction is executed.
Page 389 CALL, CALLP Function (1) When the CALL (P) instruction is executed, executes the subroutine program of the program specified by Pn. The CALL (P) instruction can execute subroutine programs specified by a pointer within the same program file and subroutine programs specified by a common pointer. Main routine Subroutine program...
Page 390 CALL, CALLP (4) The number of function devices to be used by a subroutine program must be identical to the number of arguments in the CALL (P) instruction. Also, the types of the function device and CALL (P) argument used should be identical. (5) Device numbers specified by the CALL (P) instruction should not overlap.
Page 391 CALL, CALLP [Operation performed after subroutine program execution] Immediately after the At the time of Before the execution execution of CALL subroutine program After the execution of subroutine program instruction execution of RET instruction 33 *2 1 *2 100 *2 Transfer 1000 1000...
Page 392: Return From Subroutine Programs
Program Example (1) The following program executes a subroutine program with argument when X20 is turned ON. [Ladder Mode] [List Mode] Device Step Instruction 7.6.4 Return from subroutine programs 7.6.4 High Basic Process Redundant Universal LCPU performance Setting Internal Devices R, ZR Constants Other...
Page 393: Fcall, Fcallp
FCALL, FCALLP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code After the CALL(P), FCALL (P), ECALL (P), EFCALL (P) or XCALL 4211 instruction was executed, an END, FEND, GOEND, or STOP instruction was excected prior to the RET instruction.
Page 394 FCALL, FCALLP (b) The operation results for the individual coil instructions following non-execution processing will be as follows, regardless of the ON/OFF status of the individual contacts: OUT instruction............Forced OFF SET instruction RST instruction SFT instruction ....Maintains status Basic instructions Application instructions PLS instruction...
Page 395 FCALL, FCALLP (4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with corresponding to the function device. The contents to the devices specified by are as indicated below. (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. (b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding devices.
Page 396 FCALL, FCALLP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The device specified for the argument cannot be secured for the data 4101 size.
Page 397: Ecall, Ecallp
ECALL, ECALLP 7.6.6 ECALL, ECALLP Subroutine calls between program files 7.6.6 ECALL, ECALLP High Basic Process LCPU Redundant Universal performance Command ECALL ECALL File name Command ECALLP ECALLP File name Command ECALL ECALL File name Command ECALLP ECALLP File name File name: Name of the program file to be called (character string) : Head pointer number of a subroutine program (Device name) : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)
Page 398 ECALL, ECALLP (4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function device with . The contents of the devices specified by are as indicated below. [MAIN] [ABC] (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. (b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding devices.
Page 399 ECALL, ECALLP Incorrect operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D1 is used in the subroutine program. [Program example] [Operation performed after subroutine program execution] At the time of Immediately after the Before the execution subroutine program...
Page 400 ECALL, ECALLP [Operation performed after subroutine program execution] Immediately after the At the time of Before the execution execution of ECALL subroutine program After the execution of of subroutine program instruction execution RET instruction 33 *2 1 *2 Transfer 100 *2 Transfer 1000 1000...
Page 401: Efcall, Efcallp
EFCALL, EFCALLP Program Example (1) The following program executes program block P0 of the program A-LINE when X20 is turned ON. [Ladder Mode] [List Mode] Device Step Instruction [MAIN] [A-LINE] Step Instruction Device 7.6.7 EFCALL, EFCALLP Subroutine output OFF calls between program files 7.6.7 EFCALL, EFCALLP High...
Page 402 EFCALL, EFCALLP Function (1) When the EFCALL(P) instruction is executed, the non-execution processing of the subroutine program of the pointer designated by Pn is performed. The EFCALL (P) can also be used to call a subroutine program that uses a local pointer from a different program file.
Page 403 EFCALL, EFCALLP (3) If the EFCALL(P) instruction is used in conjunction with the ECALL(P) instruction, non-execution processing of a subroutine program is performed when the execution command is turned OFF, enabling forcible turning OFF of the OUT instruction and the PLS instruction (including P instructions).
Page 404 EFCALL, EFCALLP (6) When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function device with [MAIN] [ABC] (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. (b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding devices.
Page 405 EFCALL, EFCALLP (9) Up to 16 levels of nesting can be used with the EFCALL (P) instruction. However, this 16 levels is the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions. ECALL "ABC" P0 EFCALL "ABC"...
Page 406: Subroutine Program Calls
XCALL 7.6.8 XCALL Subroutine program calls Ver. High Basic Process LCPU Redundant Universal performance 7.6.8 XCALL • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command XCALL XCALL : Head pointer number of a subroutine program (Device name) : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Setting Internal Devices...
Page 407 XCALL [ON/OFF timing of X0] (1) Turning X0 ON (3) Turning X0 OFF (OFF OFF) (2) During X0 is ON Time during X0 is ON (2) does not include the time when turning X0 ON (1). Component Operation of XCALL instruction •...
Page 408 XCALL [Main routine program] XCALL Occupies from D30 to D33 (Transfer to FD2). Occupies from D0 to D3 (Transfer to FD1). Occupies M0 (Transfer to FX0). can be used by the XCALL instruction. (5) The number of function devices used by a subroutine program must be identical to the number of arguments in the XCALL instruction.
Page 409: Refresh
Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The device specified for the argument cannot be secured for the data 4101 size.
Page 410 Function (1) Use the COM instruction for the following purposes. (a) To reduce the time required to send/receive data to/from the remote I/O stations. (b) To ensure data communication with a CPU module on another station when two CPU modules perform operations using different scan times.
Page 411: Select Refresh
2) In cases where the remote station scan time is longer than the scan time of the host station, the COM instruction used at the remote station side can avoid the occurrence of timing failure in which the data cannot be fetched, as shown in (a).
Page 412 (1) The COM instruction is used to perform I/O refresh at any timing during execution of a sequence program. (2) The following processing can be performed with the COM instruction. Processing item QCPU LCPU I/O refresh CC-Link refresh CC-Link IE Controller Network refresh CC-Link IE Field Network refresh MELSECNET/H refresh Auto refresh of intelligent function modules...
Page 413 (b) Set an execution status for each processing in SD778. Set an execution status for each bit of SD778 as shown below. [ QCPU] Bit of SD778 Executed Not Executed b0 to b6 SD778 I/O refresh CC-Link refresh CC-Link IE Controller Network, MELSECNET/H refresh Auto refresh of intelligent function module...
Page 414: Ccom, Ccomp
CCOM, CCOMP (5) At the point of the execution of the COM instruction, the CPU module temporarily stops the processing of the sequence program, and performs specified processing. Execution of COM Execution of COM instruction instruction Specified processing Specified processing (6) The COM instruction can be used in a sequence program any number of times.
Page 415: Index Modification Of Entire Ladder
IX, IXEND Program Example (1) Turning on M0 enables the program to execute the select refresh, while turning off M0 disables the program to execute the select refresh. [Ladder Mode] [List Mode] Instruction Device Step 7.6.12 IX, IXEND Index modification of entire ladder 7.6.12 IX, IXEND High...
Page 416 IX, IXEND (2) Index modification for device numbers is accomplished in the manner as below: By setting a modification value to each of the devices, the set modification values are added to the all device numbers of the devices used in the ladder between the IX and IXEND instructions.
Page 417 IX, IXEND Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The IX and IXEND instructions are not used as a pair. 4231 After the IX instruction was executed, the END, FEND, GOEND, or STOP instruction was executed prior to the IXEND instruction.
Page 418: Of Entire Ladders
IXDEV, IXSET 7.6.13 IXDEV, IXSET Designation of modification values in index modification of entire ladders 7.6.13 IXDEV, IXSET High Basic Process LCPU Redundant Universal performance IXDEV IXDEV IXSET IXSET Dummy contact Offset designation sections : Head number of the devices where index modification data is stored (pointer only) P (Pointer) : Head number of the devices where index modification data will be stored (except a pointer) (BIN 16 bits) Setting...
Page 419 IXDEV, IXSET (9) The dummy contacts in the offset specifying part are valid for only LD and AND located within the range of the IXDEV- IXSET instructions. The IXDEV-IXSET instructions will not be executed if other instructions are described. Example IXDEV Non-execution processing (outputs OFF) Non-execution processing (ignored)
Page 420: Data Table Operation Instructions
FIFW, FIFWP Data Table Operation Instructions 7.7.1 FIFW, FIFWP Writing data to the data table 7.7.1 FIFW, FIFWP High Basic Process Redundant Universal LCPU performance Command FIFW FIFW Command FIFWP FIFWP : Data to be written into the table or the number of the device where the data is stored (BIN 16 bits) : Head number of the table (BIN 16 bits) Internal Devices Setting...
Page 421: Fifr, Fifrp
FIFR, FIFRP Program Example (1) The following program stores the data at D0 to the data table following R0 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Table Table Number of stored data blocks 4321 4321 Data table range (2) The following program stores the data at X20 to X2F to data table of D38 to D44 table when X1B is turned ON, and, if...
Page 422 FIFR, FIFRP Function (1) Stores the oldest data ( +1) input to the table designated by at the device designated by After the execution of the FIFR instruction, the data in the table is all compressed up by one block. Data table Data table Number of stored...
Page 423: Fpop, Fpopp
FPOP, FPOPP (2) The following program stores the data at D0 in the data table D38 to D43, and, when the table stores 5 data, stores the data at D39 of the data table in R0, when X1C is turned ON. [Ladder Mode] [List Mode] Step...
Page 424 FPOP, FPOPP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 The FPOP instruction was executed when the value of was 0.
Page 425: Deletion Of Data From Data Tables
FDEL, FDELP, FINS, FINSP 7.7.4 FDEL, FDELP Deletion of data from data tables 7.7.4 FINS, FINSP Insertion of data in data tables FDEL, FDELP, FINS, FINSP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of FDEL/FINS. Command FDEL, FINS Command FDELP, FINSP...
Page 426 FDEL, FDELP, FINS, FINSP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The FDEL or FINS instruction was executed when n = 0.
Page 427 FDEL, FDELP, FINS, FINSP (2) The following program inserts the data at D0 into the third position at the table R0 to R7 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Data table Data table X10:ON 1234 1234...
Page 428: Buffer Memory Access Instruction
FROM, FROMP, DFRO, DFROP Buffer memory access instruction 7.8.1 FROM, FROMP Reading 1-word data from the intelligent function module DFRO, DFROP Reading 2-word data from the intelligent function module 7.8.1 FROM, FROMP, DFRO, DFROP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of FROM/DFRO.
Page 429 FROM, FROMP, DFRO, DFROP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code An error has been detected in an intelligent function module at the 1402 execution of the instruction.
Page 430: Dto, Dtop
TO, TOP, DTO, DTOP Remark 1. The value of n1 is specified by the upper 3 digits of hexadecimal 4 digits which represent the head I/O number of an intelligent function module. QCPU Power QY41 supply QX10 QX10 QX10 QX10 QY10 QY10 module 0000...
Page 431 TO, TOP, DTO, DTOP Function Writes the data stored in n3 points starting from the device designated by into the area starting from buffer memory address designated by n2 of the intelligent function module designated by n1. Intelligent function module buffer memory CPU module Device designated...
Page 432 TO, TOP, DTO, DTOP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code An error has been detected in an intelligent function module at the 1402 execution of the instruction.
Page 433 TO, TOP, DTO, DTOP Remark 1. The value of n1 is specified by the upper 3 digits of hexadecimal 4 digits which represent the head I/O number of an intelligent function module. QCPU Power QY41 supply QX10 QX10 QX10 QX10 QY10 QY10 module 0000...
Page 434: Display Instructions
Display instructions 7.9.1 Print ASCII code 7.9.1 High Basic Process LCPU Redundant Universal performance Command : ASCII code or head number of the devices where the ASCII code is stored (character string) : Head number of the output module to which the ASCII code will be output (bits) Internal Devices Setting Constants...
Page 435 (b) If SM701 is OFF, everything from the device designated by to the 00 code will be the target of the operation. Device where ASCII code is stored Upper 8 bits Lower 8 bits Output Y b8 b7 Head of output ASCII code output Scheduled Printer or...
Page 436: Prc
Program Example (1) The following program converts the string "ABCDEFGHIJKLMNOP" to ASCII code when X0 is turned ON and stores it from D0 to D7, and then outputs the ASCII code at D0 to D7 to Y14 to Y1D when X3 is turned ON. [Ladder Mode] When X0 turns ON, converts “ABCDEFGHIJKLMOP”...
Page 437 Function (1) Outputs comment (ASCII code) at device designated by to output module designated by The number of characters output differs according to the ON/OFF status of SM701. • When SM701 is OFF: Comment is 32 characters • When SM701 is ON : Comment is the upper 16 characters The number of points used by the output module is 10 points from the Y address designated by Comment at X1 Output Y...
Page 438 (2) Output signals from the output module are transmitted at the rate of 30 ms per character. For this reason, the time required to the completion of the transmission of the designated number of characters will be 30 n (ms). At 10ms interrupt intervals, the PRC instruction executes data output, strobe signal ON, and strobe signal OFF.
Page 439: Ledr
LEDR Program Example (1) Program which outputs the comment of Y60 to Y30 to Y39 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 7.9.3 LEDR Error display and annunciator reset 7.9.3 LEDR High Basic Process LCPU Redundant Universal performance Command...
Page 440 LEDR (b) For CPUs with an LED display at the front The following operations will be conducted when the LEDR instruction is executed: 1) The F number being displayed at the front of the CPU module will be reset. 2) "USER" LED flickers, and is turned off. 3) The annunciators (F) stored in SD62 and SD64 are reset, and the F numbers for SD65 to SD79 are compressed forwards.
Page 441 LEDR Remark 1. The defaults for the error item numbers set in special registers SD207 to SD209 and order of priority are given in the table below: Factor number Priority Meaning Remarks (Hexadecimal) AC DOWN Power supply cut SINGLE PS.DOWN Redundant base unit power supply voltage drop (QCPU only) SINGLE PS.ERROR Redundant power supply module fault (QCPU only)
Page 442: Debugging And Failure Diagnosis Instructions
CHKST, CHK 7.10 Debugging and failure diagnosis instructions 7.10.1 CHKST, CHK Special format failure check 7.10.1 CHKST, CHK High Basic Process LCPU Redundant Universal performance Command CHKST CHKST Check condition (Only a contact is valid; b contact is ignored) Only input (X) can be used Up to 150 contacts can be connected Setting Internal Devices...
Page 443 CHKST, CHK (b) The contact instruction prior to the CHK instruction does not control the execution of the CHK instruction, but rather sets the check conditions. Advance command (X4) Advance operation (Y50) Advance Retract operation (Y51) Retract Advance end sensor (X0) Retract end sensor (X1) turns ON at the detection turns ON at the detection...
Page 444 CHKST, CHK (2) Depending on the designated contact, the CHK instruction undergoes processing identical to that shown for the ladder below: CHKST (Detection by both advance and retraction end sensors during advance operation of the conveyor) Max. 150 contacts X +1 Y SM80 Coil No.
Page 445 CHKST, CHK (7) Place LD and AND instructions prior to the CHK instruction to establish a check condition. Check conditions cannot be set using other contact instructions. If a check condition has been set with LDI or ANI, the processing for the check condition they specify will not be conducted.
Page 446: Chkcir, Chkend
CHKCIR, CHKEND 7.10.2 CHKCIR, CHKEND Changing check format of CHK 7.10.2 CHKCIR, CHKEND High Basic Process LCPU Redundant Universal performance When the GX Developer is used (High Performance model QCPU/Process CPU/Redundant CPU) Command CHKST Refer to CHKST Page 440, Section 7.10.1. SM400 CHKCIR CHKCIR...
Page 447 CHKCIR, CHKEND 1) If SM710 is OFF, checks will be conducted of coil numbers 1 through the end for each contact successively. [Ladder designated by CHKCIR to CHKEND] [Order of check by CPU module] X12 X14 Y42 X8 CHKST Ladder equivalent to X2 SM400 Y60 X23...
Page 448 CHKCIR, CHKEND (g) The annunciators (F) used in the CHK instruction do not actually turn ON/OFF. Even when they are monitored from an external device, the ON/OFF status cannot be checked. (h) A ladder pattern can be created up to 256 steps. Further, OUT F can use up to 9 coils.
Page 449: Character String Processing Instructions
BINDA, BINDAP, DBINDA, DBINDAP 7.11 Character string processing instructions 7.11.1 BINDA, BINDAP Conversion from BIN 16-bit data to decimal ASCII DBINDA, DBINDAP Conversion from BIN 32-bit data to decimal ASCII 7.11.1 BINDA, BINDAP, DBINDA, DBINDAP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BINDA/DBINDA.
Page 450 BINDA, BINDAP, DBINDA, DBINDAP DBINDA (1) Converts the individual digit numbers of decimal notation of the BIN 32-bit data designated by into ASCII codes, and stores the results into the area starting from the device designated by b8b7 ASCII code for billions place Sign ASCII code for ten-millions place ASCII code for hundred-mi l l i o ns pl a ce...
Page 451: Binha, Binhap
BINHA, BINHAP, DBINHA, DBINHAP [Operation] Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON. Because SM701 is OFF, the PR instruction will output ASCII code until 00 is encountered. b8 b7 (space) (space) 5126 Y40 to Y48 BIN value...
Page 452 BINHA, BINHAP, DBINHA, DBINHAP Function BINHA (1) Converts the individual digit numbers of hexadecimal notation of the BIN 16-bit data designated by into ASCII codes, and stores the results into the area starting from the device designated by b8b7 ASCII code for the 3rd digit ASCII code for the 4th digit ASCII code for the 1st digit ASCII code for the 2nd digit...
Page 453 BINHA, BINHAP, DBINHA, DBINHAP Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The range of the device specified in exceeds the range of the 4101 ––...
Page 454: Bcdda, Bcddap
BCDDA, BCDDAP, DBCDDA, DBCDDAP 7.11.3 BCDDA, BCDDAP Conversion from BCD 4-digit data to decimal ASCII data 7.11.3 DBCDDA, DBCDDAP Conversion from BCD 8-digit data to decimal ASCII data BCDDA, BCDDAP, DBCDDA, DBCDDAP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BCDDA/DBCDDA. Command BCDDA, DBCDDA Command...
Page 455 BCDDA, BCDDAP, DBCDDA, DBCDDAP DBCDDA (1) Converts the individual digit numbers of hexadecimal notation of the BCD 8-digit data designated by into ASCII codes, and stores the results into the area starting from the device designated by b8b7 ASCII code for millions place ASCII code for ten-millions place ASCII code for ten-thousands place ASCII code for hundred-thousands place...
Page 456 BCDDA, BCDDAP, DBCDDA, DBCDDAP Program Example (1) The following program uses the PR instruction to convert BCD 4-digit data (the value at W0) to decimal, and outputs it in ASCII format to Y40 to Y48. [Ladder Mode] [List Mode] Step Instruction Device [Operation]...
Page 457: Dabin, Dabinp
DABIN, DABINP, DDABIN, DDABINP 7.11.4 DABIN, DABINP Conversion from decimal ASCII to BIN 16-bit data DDABIN, DDABINP Conversion from decimal ASCII to BIN 32-bit data 7.11.4 DABIN, DABINP, DDABIN, DDABINP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DABIN/DDABIN. Command DABIN, DDABIN Command...
Page 458 DABIN, DABINP, DDABIN, DDABINP For example, if the ASCII code of -1234543210 is designated for the area starting from , the operation result would be stored at +1 and in the following manner: b8b7 12 34 3 2 1 0 (2) The ASCII data designated by +5 can be in the range of from -2147483648 to 2147483647.
Page 459: Habin, Habinp
HABIN, HABINP, DHABIN, DHABINP (2) The following program converts the decimal, 10-digit ASCII data and sign set at D20 through D25 to BIN values and stores the result at D10 and D11. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8b7 (space) (space)
Page 460 HABIN, HABINP, DHABIN, DHABINP DHABIN (1) Converts hexadecimal ASCII data stored in the area starting from the device number designated by into BIN 32-bit data, and stores it in the device number designated by b8b7 ASCII code for the 7th digit ASCII code for the 8th digit b16 b15 ASCII code for the 5th digit...
Page 461: Dabcd, Dabcdp
DABCD, DABCDP, DDABCD, DDABCDP (2) The following program converts the hexadecimal, 8-digit ASCII data set at D20 to D23 to BIN values, and stores the result at D10 and D11. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8b7 1 3 3 9 1 9 7 2 6 4 Regarded as 4FD28750 BIN value...
Page 462 DABCD, DABCDP, DDABCD, DDABCDP DDABCD (1) Converts decimal ASCII data stored in the area starting from the device designated by to 8-digit BCD data, and stores it into the area starting from the device designated by ASCII code for millions place ASCII code for ten-millions place ASCII code for ten-thousands place ASCII code for hundred-thousands place...
Page 463: Comrd, Comrdp
COMRD, COMRDP (2) The following program converts the decimal ASCII data set at D20 to D23 into 8-digit BCD data, stores the result at D10 and D11, and also outputs it to from Y40 to Y5F. [Ladder Mode] Outputs the converted BCD value to a display device.
Page 464 COMRD, COMRDP For example, if the comment for the device designated by were "NO. 1 LINE START," the operation results would be stored following as follows: b8b7 Comment at (space) NO.1 LINE START (space) (space) (space) (space) (2) If no comment has been registered for the device specified by despite the fact that the comment range setting is made, all of the characters for the comment are processed as "20 "...
Page 465: Len, Lenp
LEN, LENP Program Example (1) The following program stores the comments set at D100 into the area starting from W0 as ASCII when X1C is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8 b7 (space) Comment at D100 (space) LINE A TARGET...
Page 466 (1) The following program outputs the length of the character string from D0 to Y40 to Y4F as BCD 4-digit values. [Ladder Mode] Outputs the length of character string to a display device. [List Mode] Step Instruction Device [Operation] b8b7 BCD conversion 0 0 1 0 BCD value "MITSUBISHI" (Characters "ABC" that follow 00 are ignored)
Page 467: Dstr, Dstrp
STR, STRP, DSTR, DSTRP 7.11.9 STR, STRP Conversion from BIN 16-bit data to character string DSTR, DSTRP Conversion from BIN 32-bit data to character string Ver. High Basic Process Redundant Universal LCPU 7.11.9 performance STR, STRP, DSTR, DSTRP • Basic model QCPU: The serial number (first five digits) is "04122"...
Page 468 STR, STRP, DSTR, DSTRP (b) If the setting for the number of digits after the decimal fraction is anything other than "0", "2E " (.) will automatically be stored at the position before the first of the specified number of digits. Total number of digits Number of digits 1 2 3 4...
Page 469 STR, STRP, DSTR, DSTRP (5) After conversion, character string data is stored at the device number following as indicated below: (a) The sign "20 " (space) will be stored if the BIN data is positive, and the sign "2D " (minus sign) will be stored if it is negative.
Page 470 STR, STRP, DSTR, DSTRP Program Example (1) The following program converts the BIN 16-bit data stored at D10 when X0 is turned ON in accordance with the digit designation of D0 and D1, and stores the result from D20 to D23. [Ladder Mode] Sets the data.
Page 471: Dval, Dvalp
VAL, VALP, DVAL, DVALP 7.11.10 VAL, VALP Conversion from character string to BIN 16-bit data DVAL, DVALP Conversion from character string to BIN 32-bit data Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is 7.11.10 VAL, VALP, DVAL, DVALP "04122"...
Page 472 VAL, VALP, DVAL, DVALP (5) The sign "20 " will be stored if the numerical value is positive, and the sign "2D " will be stored if it is negative. (6) "2E " is set for the decimal point. (7) The total number of digits stored at amounts to all characters expressing numerical values (including signs and decimal points).
Page 473 VAL, VALP, DVAL, DVALP (8) In cases where the character string designated by contains "20 " (space) or "30 " (0) between the sign and the first numerical value other than "0", these "20 " and "30 " are ignored in the conversion into a BIN value. Total number of digits Number of digits 6 5 4 3 .
Page 474: Estr, Estrp
ESTR, ESTRP [Operation] b8b7 1654 Total number of digits Number of digits in decimal fraction (2) The following program reads the character string data stored from D20 to D24 as an integer, converts it to a BIN value, and stores it at D0 when X0 is ON. [Ladder Mode] [List Mode] Step...
Page 475 ESTR, ESTRP When using decimal point format b8 b7 Decimal point format ASCII code for the ASCII code for the sign (total number of digits -1) Total number of digits th digit Number of digits in decimal fraction ASCII code for the ASCII code for the (total number of digits -3) (total number of digits -2)
Page 476 ESTR, ESTRP 3) If the number of digits following the decimal point has been set at any value other than "0", "2E " (.) will automatically be stored at the position before the first of the specified number of digits. 0: Decimal point format 8 (Total number of digits) Total number of digits...
Page 477 ESTR, ESTRP (a) The total number of digits that can be designated by +1 is as shown below: When the number of decimal fraction digits is "0" ......Number of digits (max.: 24) When the number of decimal fraction digits is other than "0" ......Number of digits (max.: 24) (Number of decimal fraction digits + 7) (b) The number of digits of dicimal fraction part that can be designated by...
Page 478 ESTR, ESTRP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code value is not within the following range: -126 0, 2 | <...
Page 479: Eval, Evalp
EVAL, EVALP (2) The following program converts the 32-bit floating decimal point type real number data which had been stored at D0 and D1 in accordance with the conversion designation that is being stored at R10 to R12, and stores the result following D10 when X1C goes ON.
Page 480 EVAL, EVALP (2) The designated character string can be converted to 32-bit floating point type real number data either in the decimal point format or the exponent format. b8 b7 ASCII code for the 1st character ASCII code for the sign ASCII code for the 3rd character ASCII code for the 2nd character +2 ASCII code for the 5th character...
Page 481 EVAL, EVALP (b) When using exponent format b8b7 (space) -1 . 350 34 E- 2 32-bit floating-point real number . 3 5 0 3 4 1 2 E These are cut (4) In the decimal point format, if "2B " (+) is specified for the sign or if the designation of sign is omitted, conversion is made assuming a positive value.
Page 482 EVAL, EVALP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The integer portion or the decimal fraction portion contains a character other than one in the range from "30 "...
Page 483: Asc, Ascp
ASC, ASCP [Operation] b8b7 (space) (space) D101 D100 1 . 2 3 4 5 E -2 1 . 2 3 4 5 E Ignored Ignored 7.11.13 ASC, ASCP Conversion from hexadecimal BIN to ASCII 7.11.13 ASC, ASCP High Basic Process Redundant Universal LCPU performance...
Page 484 ASC, ASCP (3) Processing will be performed accurately even if the device range where BIN data to be converted is being stored overlaps with the device range where the converted ASCII data will be stored. b8b7 (4) If an odd number of characters has been designated by n, the ASCII code "00 "...
Page 485: Hex, Hexp
HEX, HEXP 7.11.14 HEX, HEXP Conversion from ASCII to hexadecimal BIN 7.11.14 HEX, HEXP High Basic Process Redundant Universal LCPU performance Command Command HEXP HEXP : Head number of the devices where a character string to be converted to BIN data is stored (character string) : Head number of the devices where the converted BIN data will be stored (BIN 16 bits) : Number of characters to be stored (BIN 16 bits) Internal Devices...
Page 486 HEX, HEXP (4) If the number of characters designated by n is not divisible by 4, "0" will be automatically stored after the designated number of characters in the final device number of the devices which are storing the converted BIN values. b8b7 Value "0"...
Page 487: Extracting Character String Data From The Right
RIGHT, RIGHTP, LEFT, LEFTP 7.11.15 RIGHT, RIGHTP Extracting character string data from the right LEFT, LEFTP Extracting character string data from the left 7.11.15 RIGHT, RIGHTP, LEFT, LEFTP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of RIGHT/LEFT. Command RIGHT, LEFT Command...
Page 488 RIGHT, RIGHTP, LEFT, LEFTP LEFT (1) Stores n number of characters from the left side of the character string (the beginning of the character string) being stored in devices starting from that whose number is designated by , in devices starting from that whose number designated by b8b7 b8b7...
Page 489: Midr, Midrp
MIDR, MIDRP, MIDW, MIDWP (2) The following program stores the number of characters corresponding to the value being stored in D0 from the left of the character string data being stored at D100 to the area starting from R10 when X1C is turned ON. [Ladder Mode] [List Mode] Step...
Page 490 MIDR, MIDRP, MIDW, MIDWP (2) The NULL code (00 ) indicating the end of the character string is automatically added to the end of the character string. Refer to Page 90, Section 3.2.5 for the format of the character string data. (3) No processing will be conducted if the number of characters designated by +1 is "0".
Page 491 MIDR, MIDRP, MIDW, MIDWP (4) If the number of characters designated by +1 exceeds the final character from the character string data designated by , data will be stored up to the final character. Before execution b8b7 b8b7 "ABCDEFGHI" After execution "012345678"...
Page 492 MIDR, MIDRP, MIDW, MIDWP For MIDW instruction Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The value of exceeds the number of characters specified by +1 value exceeds the number of characters for 4101 –– +0 value is 0. "00 "...
Page 493: Instr, Instrp
INSTR, INSTRP 7.11.17 INSTR, INSTRP Character string search 7.11.17 INSTR, INSTRP High Basic Process Redundant Universal LCPU performance Command INSTR INSTR Command INSTRP INSTRP : Character string to be searched or head number of the devices where the character string to be searched is stored (character string) : Character string in which a search is performed or head number of the devices where the character string is stored (character string) : Head number of the devices where the result of search will be stored (BIN 16 bits) : Location to start the search (BIN 16 bits)
Page 494: Strins, Strinsp
STRINS, STRINSP Program Example (1) The following program searches from the 5th character from the left of the character string data stored in devices starting from R0 for the character string data in devices starting from D0, and stores the results at D100 when X0 goes ON. [Ladder Mode] [List Mode] Step...
Page 495 STRINS, STRINSP Function (1) This instruction inserts the character string data specified by to the nth device (insert position) from the initial character string data stored in the devices specified by Insert position: n b8b7 Shifts the third character and up by the number of b8b7 characters specified by to the left and inserts...
Page 496: Strdel, Strdelp
STRDEL, STRDELP Program Example (1) The following program inserts the character string data stored in the device D0 and up to the fourth device from the initial character string data stored in D20 and up, when M0 is turned on. [Ladder Mode] [List Mode] Instruction...
Page 497 STRDEL, STRDELP Function (1) This instruction deletes n2 characters data in the devices specified by starting from the device (insert position) specified by n1. Device position where character string data to be deleted: n1 Number of characters to be deleted: n2 Shifts the n1+n2th characters and up, which are stored after the devices whose characters Stores the NULL code (00...
Page 498: Emod, Emodp
EMOD, EMODP [Operation] D0 character string P R O D D0 character string P R O G R A M A B C D D0 character string P R O G R A M A B C D Seven characters to be deleted Fourth character to be deleted 7.11.20 EMOD, EMODP...
Page 499 EMOD, EMODP (2) The 7th digit of the significant digits being stored at +1 and +2 is rounded off to make a 6-digit number. . 2 3456789 1234570 123456789 Rounded off 1234570 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 500 EREXP, EREXPP 7.11.21 EREXP, EREXPP From BCD format data to floating-point data 7.11.21 EREXP, EREXPP High Basic Process Redundant Universal LCPU performance Command EREXP EREXP Command EREXPP EREXPP : Head number of the devices where BCD type floating point format data is stored (BIN 16 bits) : Decimal fraction digits data (BIN 16 bits) : The device where the converted 32-bit floating point real number data will be stored (real number) Setting...
Page 501 EREXP, EREXPP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The data format in the device specified by is not 0 or 1.
Page 502 SIN, SINP 7.12 Special function instructions 7.12.1 SIN, SINP SIN operation on floating-point data (Single precision) Ver. High Basic Process Redundant Universal LCPU performance 7.12.1 SIN, SINP • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command SINP...
Page 503 SIND, SINDP Program Example (1) The following program conducts a SIN operation on the angles stored in the four BCD digits from X20 to X2F and stores the results at D0 and D1 as 32-bit floating decimal point type real numbers. [Ladder Mode] Inputs an angle used for SIN operation (...
Page 504 SIND, SINDP (2) Angles designated at are set in radian units (degrees / 180). For conversion between degrees and radian values, see the RADD and DEGD instructions. (3) When the operation results in -0 or an underflow, the result is processed as 0. Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 505 COS, COSP 7.12.3 COS, COSP COS operation on floating-point data (Single precision) Ver. High Basic Process LCPU Redundant Universal performance 7.12.3 COS, COSP • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command COS P COSP : Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data is stored (real number) : Head number of the devices where the operation result will be stored (real number)
Page 506 COSD, COSDP Program Example (1) The following program performs a COS operation on the angle data designated by the 4 BCD digits from X20 to X2F, and stores results as 32-bit floating decimal point type real numbers at D0 and D1. [Ladder Mode] Inputs an angle used for COS operation (...
Page 507 COSD, COSDP Function (1) The COS (cosine) value of the angle specified by is calculated and its result is stored into the device specified by COS ( 64-bit floating-point 64-bit floating-point real number real number (2) Angles designated at are set in radian units (degrees / 180).
Page 508 TAN, TANP [Operations involved when X20 to X2F designate a value of 60] Conversion Conversion to D23 D22 to BIN floating-point 0 6 0 BIN value BCD value 64-bit floating-point FLTD real number Conversion to radian RADD D13 D12 D3 D2 SIN operation 1.047198 0.500000...
Page 509 TAN, TANP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified device value is not within the following range: -126 4100 0, 2...
Page 510 TAND, TANDP 7.12.6 TAND, TANDP TAN operation on floating-point data (Double precision) 7.12.6 TAND, TANDP High Basic Process Redundant Universal LCPU performance Command TAND TAND Command TANDP TANDP : Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices Setting...
Page 511 ASIN, ASINP Program Example (1) The following program performs a TAN operation on the angle data set by the 4 BCD digits from X20 to X2F, and stores the results as 64-bit floating decimal point type real numbers at D0 to D3. [Ladder Mode] Inputs an angle used for TAN operation (...
Page 512 ASIN, ASINP Function (1) Returns the SIN angle of the SIN value designated by , and stores operation results at word device designated by SIN ( 32-bit floating-point 32-bit floating-point real number real number (2) The SIN value designated by can be in the range from -1.0 to 1.0.
Page 513 ASIND, ASINDP [Operations involved when the D0 and D1 value is 0.5] operation 0 . 5 0 . 5 2 3 5 9 8 8 32-bit floating-point ASIN 32-bit floating-point real number real number Conversion to angle Conversion BCD operation toBIN 0 0 3 0 32-bit floating-point...
Page 514 ASIND, ASINDP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The value specified by is within the double-precision floating-point 4100 ––...
Page 515 ACOS, ACOSP 7.12.9 ACOS, ACOSP Arc cosine operation on floating-point data (Single precision) 7.12.9 ACOS, ACOSP High Basic Process Redundant Universal LCPU performance Command ACOS ACOS Command ACOSP ACOSP : COS value of which the COS (inverse cosine) value is obtained or head number of the devices where the COS value is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices Setting...
Page 516 ACOSD, ACOSDP Program Example (1) The following program seeks the inverse cosine of the 32-bit floating decimal point real number at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by COS operation ( Converts the radian value into an angle (...
Page 517 ACOSD, ACOSDP Function (1) The angle is calculated from the COS (cosine) value specified by is and its result is stored into the device specified by COS ( 64-bit floating-point 64-bit floating-point real number real number (2) The COS value designated by can be in the range of from -1.0 to 1.0.
Page 518 ATAN, ATANP [Operations involved when the D0 to D3 value is 0.5] D3 D2 D13 D12 COS operation 1.047198 64-bit floating-point 64-bit floating-point ACOSD real number real number Conversion to angle DEGD Conversion BCD operation D23 D22 to BIN 0 0 6 0 BIN value BCD value 64-bit floating-point...
Page 519 ATAN, ATANP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 –– ––...
Page 520 ATAND, ATANDP 7.12.12 ATAND, ATANDP Arc tangent operation on floating-point data (Double precision) 7.12.12 ATAND, ATANDP High Basic Process Redundant Universal LCPU performance Command ATAND ATAND Command ATANDP ATANDP : TAN value of which the TAN (inverse tangent) value is obtained or head number of the devices where the TAN value is stored (real number) : Head number of the devices where the operation result will be stored (real number) Internal Devices Setting...
Page 521 RAD, RADP Program Example (1) The following program seeks the inverse tangent of the 64-bit floating decimal point real number at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by TAN operation ( Converts the radian value into an angle (...
Page 522 RAD, RADP Function (1) Converts units of angle size from angle units designated by to radian units, and stores result at device number designated by )rad 32-bit floating-point 32-bit floating-point real number real number (2) Conversion from degree to radian units is performed according to the following equation: Radian unit = Degree unit Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into...
Page 523 RADD, RADDP 7.12.14 RADD, RADDP Conversion from floating-point angle to radian (Double precision) 7.12.14 RADD, RADDP High Basic Process Redundant Universal LCPU performance Command RADD RADD Command RADDP RADDP : Angle to be converted to radian units or head number of the devices where the angle is stored (real number) : Head number of the devices where the value converted in radian units will be stored (real number) Setting Internal Devices...
Page 524 DEG, DEGP Program Example (1) The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians, and stores results as 64-bit floating decimal point type real number at D20 to D23. [Ladder Mode] Inputs an angle to be converted into a radian value ( Converts the input angle into a 64-bit...
Page 525 DEGD, DEGDP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 4100 –– ––...
Page 526 DEGD, DEGDP Function (1) The unit expressing the size of an angle is converted into the degree unit from the radian unit specified by , and its result is stored into the device specified by )rad 64-bit floating-point 64-bit floating-point real number real number (2) The conversion from radians to angles is performed according to the following equation:...
Page 527 POW, POWP 7.12.17 POW, POWP Exponentiation operation on floating-point data (Single precision) Ver. High Basic Process Redundant Universal LCPU 7.12.17 performance POW, POWP • QnU(D)(H)CPU, QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command Command POWP POWP : Exponentiation recipient data or head number of the devices where the exponentiation recipient data are stored (real number) : Exponentiation data or head number of the devices where the data are stored (real number) : Head number of the devices where the operation result will be stored (real number)
Page 528 POWD, POWDP Program Example (1) The following program raises the 32-bit floating-point data type real number data specified by D0 and D1 to the data specified by (D10 and D11)th power, when X10 is turned on. Then the program stores the operation result into D20 and D21.
Page 529 SQR, SQRP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The value specified by is out of the range shown below.
Page 530 SQR, SQRP Function (1) Returns the square root of the value designated at , and stores the operation result in the device number designated at 32-bit floating-point 32-bit floating-point real number real number (2) Only positive values can be designated by .
Page 531 SQRD, SQRDP 7.12.20 SQRD, SQRDP Square root operation for floating-point data (Double precision) 7.12.20 SQRD, SQRDP High Basic Process Redundant Universal LCPU performance Command SQRD SQRD Command SQRDP SQRDP : Data of which the square root is obtained or head number of the devices where the data is stored (real number) : Head number of the devices where the operation result will be stored (real number) Setting Internal Devices...
Page 532 EXP, EXPP [List Mode] Step Instruction Device [Operations involved when value designated by X20 to X2F is 650] Conversion Conversion to D13 D12 D3 D2 SQR operation to BIN floating-point 6 5 0 25.4951 BCD value BIN value FLTD SQRD 7.12.21 EXP, EXPP Exponent operation on floating-point data (Single precision)
Page 533 EXP, EXPP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The operation result is not within the following range: ––...
Page 534 EXPD, EXPDP Conversion from natural logarithm to common logarithm In the CPU module, calculation is made using a natural logarithm. To obtain a common logarithm value, enter in, a common logarithm value divided by 0.43429. 7.12.22 EXPD, EXPDP Exponent operation on floating-point data (Double precision) 7.12.22 EXPD, EXPDP...
Page 535 EXPD, EXPDP Program Example (1) The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X31, and stores the results as a 64-bit floating decimal point real number at D0 to D3. [Ladder Mode] Inputs data used for exponent operation (...
Page 536 LOG, LOGP 7.12.23 LOG, LOGP Natural logarithm operation on floating-point data (Single precision) Ver. High Basic Process LCPU Redundant Universal 7.12.23 performance LOG, LOGP • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command LOGP LOGP : Data of which the natural logarithm is obtained or head number of the devices where the data is stored (real number)
Page 537 LOGD, LOGDP Program Example (1) The following program seeks the natural logarithm of the value "10" set by D50, and stores the result at D30 and D31. [Ladder Mode] Sets data used for natural logarithm operation ( Converts the operation data into a 32-bit floating-point real number ( Executes natural logarithm operation ( [List Mode]...
Page 538 LOGD, LOGDP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The value specified in is negative.
Page 539 LOG10, LOG10P 7.12.25 LOG10, LOG10P Common logarithm operation on floating-point data (Single precision) Ver. High Basic Process Redundant Universal LCPU 7.12.25 performance LOG10, LOG10P • QnU(D)(H)CPU, QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. Command LOG10 LOG10 Command LOG10P LOG10P...
Page 540 LOG10D, LOG10DP Program Example (1) The following program obtains the value for common logarithm of the 32-bit floating-point data type real number specified by D600 or D601, when X10 is turned on. Then the program stores the operation result into D123 or D124. [Ladder Mode] [List Mode] Device...
Page 541 RND, RNDP, SRND, SRNDP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The value specified in is negative.
Page 542 BSQR, BSQRP, BDSQR, BDSQRP Function The random number generation instruction generates random numbers conforming to a certain calculation formula. In the calculation using the formula, the result of previous calculation is used as a coefficient. The random series change instruction can change the random number generation pattern. Generates random number of from 0 to 32767, and stores at device designated by SRND Updates random number series according to the 16-bit BIN data being stored in device designated by...
Page 543 BSQR, BSQRP, BDSQR, BDSQRP Function BSQR (1) Returns the square root of the value designated at , and stores the operation result in the device number designated at Integer part Decimal fraction part (2) Values that can be designated at are BCD values with a maximum of 4 digits (from 0 to 9999).
Page 544 BSIN, BSINP [List Mode] Step Instruction Device [Operation] Transfer BSQR operation 1325 1 3 2 5 0 0 3 6 0 0 3 6 Integer part BCD value BSQR BCD value BCD value Transfer 4 0 0 5 4 0 0 5 Decimal fraction part BCD value BCD value...
Page 545 BSIN, BSINP Function (1) Calculates the SIN (sine) value of value (angle) designated by , and stores the sign of the operation result in the device designated at , and the operation result in the devices designated at +1 and Sign Integer part Decimal fraction part...
Page 546 BCOS, BCOSP [Operations involved when value designated by X20 to X2B is 590] B/ operation 5 9 0 0 0 0 1 BCD value BCD value (quotient) BSIN operation 0 2 3 0 0 0 0 1 Y60 ON BCD value BSIN BCD value (remainder)
Page 547 BCOS, BCOSP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The data specified in is not a BCD value.
Page 548 BTAN, BTANP 7.12.31 BTAN, BTANP BCD type TAN operation 7.12.31 BTAN, BTANP High Basic Process Redundant Universal LCPU performance Command BTAN BTAN Command BTANP BTANP : Data of which the TAN (tangent) value is obtained or head number of the devices where the data is stored (BCD 4 digits) : Head number of the devices where the operation result will be stored (BCD 4 digits) Setting Internal Devices...
Page 549 BASIN, BASINP [Ladder Mode] Processes so that the input angle is within 360° ( [List Mode] Step Instruction Device [Operations involved when X20 to X2B designate a value of 390] X20 B/ operation 3 9 0 0 0 0 1 BCD value BCD value (quotient)
Page 550 BASIN, BASINP Function (1) Returns the SIN (inverse sine) value of the value designated by and stores operation results (angles) at device designated by Sign Integer part Decimal fraction part (2) A sign for the operation data is set at If the operation data is a positive value, this is set at "0", and if it is a negative value, it is set at "1".
Page 551 BACOS, BACOSP [List Mode] Step Instruction Device [Operations involved when X20 to X33 designates value of 0.4753] X0 OFF BCD value Transfer BASIN operation BCD value BCD value BASIN BCD value Transfer BCD value BCD value 7.12.33 BACOS, BACOSP BCD type arc cosine operation 7.12.33 BACOS, BACOSP High...
Page 552 BACOS, BACOSP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The operation data specified in is not a BCD value.
Page 553 BATAN, BATANP [Operations involved if X0 and X20 to X33 designate a value of 0.7650] X0 ON BCD value Transfer BACOS operation BACOS BCD value BCD value BCD value Transfer BCD value BCD value 7.12.34 BATAN, BATANP BCD type arc tangent operations 7.12.34 BATAN, BATANP High...
Page 554 BATAN, BATANP Program Example (1) The following program performs a TAN operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 4-digit integer part from X20 to X2F and the BCD 4-digit decimal fraction part from X30 to X3F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
Page 555 LIMIT, LIMITP, DLIMIT, DLIMITP 7.13 Data Control Instructions 7.13.1 LIMIT, LIMITP Upper and lower limit controls for BIN 16-bit data 7.13.1 DLIMIT, DLIMITP Upper and lower limit controls for BIN 32-bit data LIMIT, LIMITP, DLIMIT, DLIMITP High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of LIMIT/DLIMIT.
Page 556 LIMIT, LIMITP, DLIMIT, DLIMITP DLIMIT (1) The function controls the output value to be stored at the device designated by ( , +1) by checking whether the input value (BIN 32 bits) designated by ( , +1) is within the range of upper and lower limit values specified by ( , S3 S3 S1 S1 and ( ,...
Page 557 BAND, BANDP, DBAND, DBANDP [Operation] • D1 becomes 500 if D0 500. Example D0 400 D1 500 • D1 becomes the value of D0 when 500 5000. Example D0 1300 D1 1300 • D1 becomes 5000 when 5000 Example D0 9600 D1 5000 (2) The following program conducts limit value controls from 10000 to 1000000 on the data set as BCD values from X20 to X3F when X0 is turned ON.
Page 558 BAND, BANDP, DBAND, DBANDP Function BAND (1) Controls the output value to be stored at the device designated by by checking whether the input value (BIN 16 bits) designated by is within the range of dead band upper and lower limit values specified by or not.
Page 559 BAND, BANDP, DBAND, DBANDP (3) The output value stored at +1 is a signed 32-bit BIN value. Therefore, if the operation results exceed the range of from -2147483648 to 2147483647, the following takes place: Dead band lower limit value ( , 1000 ....
Page 560 ZONE, ZONEP, DZONE, DZONEP 7.13.3 ZONE, ZONEP Zone control for BIN 16-bit data 7.13.3 DZONE, DZONEP Zone control for BIN 32-bit data ZONE, ZONEP, DZONE, DZONEP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ZONE/DZONE. Command ZONE, DZONE Command ZONEP, DZONEP...
Page 561 ZONE, ZONEP, DZONE, DZONEP DZONE (1) Adds bias value designated by ( , +1) or ( , +1) to input value designated by ( , +1), and stores the result at S1 S1 S3 S3 device number designated by ( , +1).
Page 562 SCL, SCLP, DSCL, DSCLP (2) The following program performs zone control by applying negative and positive bias values of -10000 to 10000 for the data set at D0 and D1 and stores the result of control at D10 and D11 when X1 is turned ON. [Ladder Mode] [List Mode] Device...
Page 563 SCL, SCLP, DSCL, DSCLP (2) If the value does not result in an integer, this instruction rounds the value to the whole number. (3) Set the X coordinate of the scaling conversion data in ascending order. (4) Set the input value within the range of the scaling conversion data (within the range of devices).
Page 564 SCL, SCLP, DSCL, DSCLP There are two searching methods that depend on whether SM750 is on or off. SM750 Searching method Range of number of searches Sequential search Number of times 32767 Binary search Number of times When the scaling conversion data are set in ascending order, the searching methods change from one to the other depending on the SM750 status.
Page 565 SCL2, SCL2P, DSCL2, DSCL2P Program Example (1) The following program executes scaling for the scaling conversion data of which the devices specified at D100 and up are set with the input value specified at D0, and then outputs the data at D20. [Ladder Mode] [List Mode] Step...
Page 566 SCL2, SCL2P, DSCL2, DSCL2P Function SCL2(P) (1) This instruction executes scaling for the scaling conversion data (16-bit data units) specified by with the input value specified by , and then stores the operation result into the devices specified by The scaling conversion is executed based on the scaling conversion data stored in the device specified by and up.
Page 567 SCL2, SCL2P, DSCL2, DSCL2P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The X coordinates are not set in ascending order.
Page 568 RSET, RSETP 7.14 File register switching instructions 7.14.1 RSET, RSETP Switching file register block numbers Ver. 7.14.1 High Basic Process Redundant Universal LCPU RSET, RSETP performance • Universal model QCPU: Models other than Q00UJCPU Command RSET RSET Command RSETP RSETP : Block number data used to change the block number or the number of the device where the block number data is stored (BIN 16 bits) Setting Internal Devices...
Page 569 QDRSET, QDRSETP Program Example (1) The following program compares R0 of block No. 0 and R0 of block No. 1. [Ladder Mode] Designates block No. 0 Executes reading R0 of block No.0 Designates block No. 1 Executes reading R0 of block No.1 Compares the read values [List Mode] Step...
Page 570 QDRSET, QDRSETP Function (1) Changes the file register file name used in the program to the file name being stored at the device designated by After the file names have been changed, all the file registers being used by the sequence program process the file register of the renamed file.
Page 571 QCDSET, QCDSETP Program Example (1) The following program compares R0 of ABC in block No. 1 and R0 of DEF in block No. 1. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Block No. 0 Block No. 1 -3216 5001 9330 -1762 -7981...
Page 572 QCDSET, QCDSETP Function (1) Changes the file register file name used in the program to the file name being stored at the device designated by After the file name change, comment data being used by the sequence program perform processing in relation to the comment data of the file name after the change.
Page 573 QCDSET, QCDSETP Program Example (1) The following program switches object file to file name ABC. QCD at drive No. 1 when X0 is ON, and to DEF. QCD at drive No. 3 when X1 is ON. [Ladder Mode] Switches to ABC at drive No. 1 Switches to DEF at drive No.
Page 574 DATERD, DATERDP 7.15 Clock instructions 7.15.1 DATERD, DATERDP Reading clock data 7.15.1 DATERD, DATERDP High Basic Process LCPU Redundant Universal performance Command DATERD DATERD Command DATERDP DATERDP : Head number of the devices where the read clock data will be stored (BIN 16 bits) Setting Internal Devices R, ZR...
Page 575 DATEWR, DATEWRP [Ladder Mode] Outputs "Year" Outputs "Month" Outputs "Day" Outputs "Hour" Outputs "Minute" Outputs "Second " Outputs "Day of week" [List Mode] Step Instruction Device [Operation] (Year) 2005 (Month, Day) Clock data 2005, 12, 24, 12:57:39, Sunday (Hour, Minute) (Second, Day of week) 7.15.2 DATEWR, DATEWRP...
Page 576 DATEWR, DATEWRP Function (1) Writes clock data stored in the device number designated by or later device number to the clock element of the CPU module. Year Month Hour Clock element Minute Second Day of week (2) Each item is set as a BIN value. (3) The "year"...
Page 577 DATE+, DATE+P [Ladder Mode] Sets "Year" Sets "Month" Sets "Day" Sets "Hour" Sets "Minute" Sets "Second " Sets "Day of week" Writes the clock data (D0 to D6) to the clock element [List Mode] Step Instruction Device [Operation] X38 X37 (Year) 2000 X28 X27...
Page 578 DATE+, DATE+P Function (1) Adds the time data designated by to the clock data designated by , and stores the result into the area starting from the device designated by Data range Data range Data range Hour Hour Hour (0 to 23) (0 to 23) (0 to 23) Minute...
Page 579 DATE-, DATE-P [List Mode] Step Instruction Device [Operation] • Time data read operation triggered by DATERDP instruction. Clock element Year Month Hour Time data Minute Second Day of week • Addition triggered by DATE+P instruction. Hour: 10 Hour: 1 D100 Hour: 11 Minute: 23 Minute: 0...
Page 580 DATE-, DATE-P (2) If the subtraction results in a negative number, 24 will be added to the result to make a final operation result. For example, if the clock time 10:42:12 were subtracted from 4:50:32, the result would not be -6:8:20, but rather would be 18:8:20.
Page 581 SECOND, SECONDP 7.15.5 SECOND, SECONDP Time data conversion (from Hour/Minute/Second to Second) 7.15.5 SECOND, SECONDP High Basic Process Redundant Universal LCPU performance Command SECOND SECOND Command SECONDP SECONDP : Head number of the devices where the clock data before conversion is stored (BIN 16 bits) : Head number of the devices where the clock data after conversion will be stored (BIN 32 bits) Internal Devices Setting...
Page 582 HOUR, HOURP [Operation] • Time data read operation triggered by DATERDP instruction. Clock device Year Month Hour Minute Time data Second Day of week • Conversion to seconds as triggered by the SECONDP instruction. D101,D100 73283 7.15.6 HOUR, HOURP Time data conversion (from Second to Hour/Minute/ Second) 7.15.6 HOUR, HOURP...
Page 583 DT=, DT<>, DT>, DT<=, DT<, DT>= Program Example (1) The following program converts the seconds stored at D0 and D1 into an hour, minute, second format, and stores the result at devices starting from D100 when X20 is turned ON. [Ladder Mode] [List Mode] Step...
Page 584 DT=, DT<>, DT>, DT<=, DT<, DT>= (b) Comparison of current date data • This instruction treats the date data specified by and the current date data as a normally open contact, and then compares the data in accordance with the value of n. •...
Page 585 DT=, DT<>, DT>, DT<=, DT<, DT>= (c) The following table shows processing details of bits to be compared. n value for n value for comparison of comparison of Date to be Processing details specified date data specified date data compared with given date data with current date data 0001...
Page 586 DT=, DT<>, DT>, DT<=, DT<, DT>= (b) Even if the dates to be compared do not exist practically, this instruction executes the comparison operation for the objects with the settable dates in accordance with the following condition. • Date A: 2006/02/30 (This date is settable, though it does not exist.) •...
Page 587 TM=, TM<>, TM>, TM<=, TM<, TM>= 7.15.8 TM=, TM<>, TM>, TM<=, Time comparison TM<, TM>= Ver. High Basic Process Redundant Universal LCPU performance 7.15.8 TM=, TM<>, TM>, TM<=, TM<, TM>= • QnU(D)(H)CPU, QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. DT=/DT<>/DT</DT<=/DT>/DT>= indicates an instruction symbol of Command...
Page 588 TM=, TM<>, TM>, TM<=, TM<, TM>= (4) This instructions sets the minute selected from 0 to 59 (0 to 59 minutes) with BIN value specified by +1 or (5) This instructions sets the second selected from 0 to 59 (0 to 59 seconds) with BIN value specified by +2 or (6) This instructions specifies the following values at n so that the data to be compared can be specified.
Page 589 TM=, TM<>, TM>, TM<=, TM<, TM>= (a) The following figure shows the comparison example of time. 0 Midnight 6:00 N00n 18:00 0 Midnight 4:50:55 14:08:58 22:47:05 The following table shows the conductive states resulting from performing the comparison operation of the dates A, B, and C shown above.
Page 590 TM=, TM<>, TM>, TM<=, TM<, TM>= (4) The following program compares the data stored in D0 with the current time data (hour), and makes Y33 be conductive status when the value of the current time data is the data value stored in D0 or larger. [Ladder Mode] [List Mode] Instruction...
Page 591 S.DATERD, SP.DATERD 7.16 Expansion Clock Instructions 7.16.1 S.DATERD, SP.DATERDReading expansion clock data Ver. Ver. Ver. High Basic Process LCPU Redundant Universal performance 7.16.1 S.DATERD, SP.DATERD • High Performance model QCPU, Process CPU, Redundant CPU: The serial number (first five digits) is "07032" or later. Command S.DATERD S.DATERD...
Page 592 S.DATERD, SP.DATERD Program Example (1) The following program outputs the following clock data as BCD values: Year ....Y70 to Y7F Month....Y68 to Y6F Day ....Y60 to Y67 Hour....Y58 to Y5F Minute....Y50 to Y57 Second .....Y48 to Y4F Week ....Y44 to Y47 Millisecond..Y38 to Y43 [Ladder Mode] Outputs "Year"...
Page 593 S.DATE+, SP.DATE+ Caution (1) This instruction reads clock data and stores those to a specified device even if a wrong clock data is set to the CPU module. (example: Feb. 30th) When setting clock data with the DATEWR instruction or GX Developer, make sure to set a correct data. (2) Time error of reading a clock data of millisecond is a maximum of 2ms.
Page 594 S.DATE+, SP.DATE+ (2) If the results of the addition of time exceed 24 hours, 24 hours will be subtracted from the sum to make the final operation result. For example, when the time 20:20:20:500 is added to 14:20:30:875, the result is not 34:40:51:375, but 10:40:51:375. Hour: 14 Hour: 20 Hour: 10...
Page 595 S.DATE+, SP.DATE+ Program Example (1) The following program adds 1 hour to the clock data read from the clock element, and stores the results into the area starting from D100 when X20 is turned ON. [Ladder Mode] Reads out the clock element data to D0 or later.
Page 596 S.DATE-, SP.DATE- 7.16.3 S.DATE-, SP.DATE- Expansion clock data subtraction operation Ver. Ver. Ver. High Basic Process Redundant Universal LCPU performance 7.16.3 S.DATE-, SP.DATE- • High Performance model QCPU, Process CPU, Redundant CPU: The serial number (first five digits) is "07032" or later. Command S.DATE- S.DATE-...
Page 597 S.DATE-, SP.DATE- Devices, +3, and +3 are not used for operation. A clock data read by S(P).DATERD instruction can be directly subtracted. Hour Minute Second Day of week Millisecond When the clock data is read by the S(P).DATERD instruction, day of week is inserted between "second" and "millisecond". If the S(P).DATE- instruction is used to read the clock data, the data can be directly used for subtraction since it does not perform the calculation for the day of the week.
Page 598 S.DATE-, SP.DATE- [List Mode] Step Instruction Device [Operation] • Time data read operation by the SP.DATERD instruction Clock element Year Month Hour Minute Time data Second Day of week Millisecond Time data • Subtraction by the SP.DATE- instruction Hour: 8 Hour: 10 D100 Hour: 22...
Page 599 7.17 Program control instructions (1) Processing when the execution type is converted with the program control instruction is as follows. Executed Instruction Execution type before change PSCAN PSTOP POFF PLOW No change-remains Output turned OFF in Scan execution type scan type execution. next scan.
Page 600 PSTOP, PSTOPP 7.17.1 PSTOP, PSTOPP Program standby 7.17.1 PSTOP, PSTOPP High Basic Process Redundant Universal LCPU performance Command PSTOP PSTOP Command PSTOPP PSTOPP : Character string for the name of the program file to be set in the stand-by status or head number of the devices where the character string data is stored (character string) Setting Internal Devices...
Page 601 POFF, POFFP 7.17.2 POFF, POFFP Program output OFF standby 7.17.2 POFF, POFFP High Basic Process Redundant Universal LCPU performance Command POFF POFF Command POFFP POFFP : File name of the program to be set in the standby status by turning OFF the output, or the device where the file name is stored (character string) Setting Internal Devices Constants...
Page 602 PSCAN, PSCANP Remark 1. Non-execution processing is identical to the processing that is conducted when the condition contacts for the individual coil instructions are in the OFF state. The operation results for the individual coil instructions following non-execution processing will be as follows, regardless of the ON/OFF status of the individual contacts: OUT instruction ....
Page 603 PLOW, PLOWP (3) Designated programs assume the scan execution type with END processing. Example When programs A, B, and C exist and program A performs "PSCAN" of program D. Execution of Program D is executed PSCAN Scan Scan (4) This instruction will be given priority even in cases when a program execution type has been designated in the parameters.
Page 604 PLOW, PLOWP Function (1) Sets the program whose file name is being stored at the device designated by in low-speed execution type. (2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as the low speed execution type. (3) Designated programs assume the low speed execution type with END processing.
Page 605 PCHK 7.17.5 PCHK Program execution status check 7.17.5 PCHK High Basic Process Redundant Universal LCPU performance LDPCHK File name PCHK Command ANDPCHK PCHK File name Command ORPCHK PCHK File name : File name of the program whose execution status will be checked (character string) Internal Devices Setting Constants...
Page 606 PCHK The PCHK instruction is in conduction when the program of the specified file name (target program) is in execution, and the instruction is in non-conduction when the program is in non-execution. When the target program is set to non-execution (stand-by type) with the POFF instruction, the PCHK instruction is in conduction while the non-execution processing of the target program is being performed.
Page 607 WDT, WDTP 7.18 Other instructions 7.18.1 WDT, WDTP Watchdog timer reset 7.18.1 WDT, WDTP High Basic Process LCPU Redundant Universal performance Command Command WDTP WDTP Internal Devices Setting R, ZR Constants Other Data Word Word –– –– Function (1) Resets watchdog timer during the execution of a sequence program. (2) Used in cases where the scan time exceeds the value set for the watchdog timer due to prevailing conditions.
Page 608 DUTY 7.18.2 DUTY Timing pulse generation 7.18.2 DUTY High Basic Process Redundant Universal LCPU performance Command DUTY DUTY : Number of scans for ON (BIN 16 bits) : Number of scans for OFF (BIN 16 bits) : User timing clock (SM420 to SM424, SM430 to M434) (bits) Internal Devices Setting Constants...
Page 609 TIMCHK [Operation] SM420 1 scan 3 scans 7.18.3 TIMCHK Time check Ver. High Basic Process Redundant Universal LCPU performance 7.18.3 TIMCHK • Basic model QCPU: The serial number (first five digits) is "04122" or later. command TIMCHK TIMCHK : Device where the measured current value will be stored (BIN 16 bits) : Device where the set value of measurement is stored (BIN 16 bits) : Device to be turned ON at time-out (bits) Internal Devices...
Page 610 ZRRDB, ZRRDBP 7.18.4 ZRRDB, ZRRDBP Direct 1-byte read from file register 7.18.4 ZRRDB, ZRRDBP High Basic Process Redundant Universal LCPU performance Command ZRRDB ZRRDB Command ZRRDBP ZRRDBP : Serial byte number for the file register to be read (BIN 32 bits) : Number of the device where the read data will be stored (BIN 16 bits) Internal Devices Setting...
Page 611 ZRWRB, ZRWRBP Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The specified device number (serial byte number) exceeds the 4101 ––...
Page 612 ZRWRB, ZRWRBP Function (1) Writes the lower 8 bits of data stored in the device designated by that does not signify a block number to the file register of the serial byte number designated by n. The upper 8 bits of data in the device designated by are ignored File register Area for block No.
Page 613 ADRSET, ADRSETP Program Example (1) The following program writes the data at the lower bits of D100 and D101 to the lower 8 bits of ZR16000 and the upper 8 bits of ZR16003 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction...
Page 614 Function (1) Stores the indirect address of the device designated by The address stored at the device designated by is used when an indirect device address is performed by the sequence program. ADRSET W100 D100 Stores the address of W100 address to D100 and D101. MOV K1234 @D100 Writes 1234 to the address specified by D100 and D101.
Page 615 Function (1) Fetches ASCII data from the 8 points of input (X) designated by , converts it to hexadecimal values and stores the result in the area starting from the device designated by Designation of the number of Input module digits to be input "0"...
Page 616 (5) The digits for the numbers actually fetched to will be stored at the device designated by , and these will be converted to the ASCII codes input at +1 and +2, converted to hexadecimal BIN values, and stored. Execution command Condition contact for the execution of KEY instruction Strobe signal (...
Page 617 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The device specified in is not an input (X) device.
Page 618 ZPUSH, ZPUSHP, ZPOP, ZPOPP 7.18.8 ZPUSH, ZPUSHP Batch save of index register 7.18.8 ZPOP, ZPOPP Batch recovery of index register ZPUSH, ZPUSHP, ZPOP, ZPOPP High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ZPUSH/ZPOP. Command ZPUSH, ZPOP Command ZPUSHP, ZPOPP : Head number of the devices to/from which contents of an index register are saved/recovered (BIN 16 bits)
Page 619 ZPUSH, ZPUSHP, ZPOP, ZPOPP • When using Universal model QCPU/LCPU Number of saves 1st nesting (20 words for the 1st nesting) 2nd nesting ZPOP (1) Recovers the contents saved in the area starting from the device designated by to the index register. (When the saved content is read out to the index register, + 0 (the number of saves made) is decreased by 1.) Operation Error...
Page 620 UNIRD, UNIRDP 7.18.9 UNIRD, UNIRDP Reading module information 7.18.9 UNIRD, UNIRDP High Basic Process Redundant Universal LCPU performance Command UNIRD UNIRD Command UNIRDP UNIRDP : Value obtained by dividing the head I/O number of the reading module information source by 16 (0 to FFn) (BIN 16 bits) : Head number of the devices where the module information will be stored (device name) : The number of points of read data (0 to 256) (BIN 16 bits) Internal Devices...
Page 621 UNIRD, UNIRDP The details of the module information are described as follows: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Individual module information Meaning Item QCPU LCPU 000: 16 points 001: 32 points 010: 48 points 011: 64 points Number of I/O points...
Page 622 UNIRD, UNIRDP Program Example (1) The following program stores the module information at I/O numbers 10 and 20 into the devices starting from D0 when X0 is turned ON. Module information Device X/Y0 module information X/Y10 module information X/Y20 module information X/YFE0 module information X/YFF0 module information [Ladder Mode]...
Page 623 UNIRD, UNIRDP (b) 32-point module for A series b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 For an A series module, all of these bits turn 0 because information is not stored. A series module Module is installed b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0...
Page 624 TYPERD, TYPERDP L series 32-point intelligent function module b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 32-point module Intelligent function module (Empty) (Empty) (Empty) No module errors Module preparation complete (Empty) Module connected b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 All 0, because information is stored in "D0".
Page 625 TYPERD, TYPERDP Function (1) This instruction reads the module information stored in the area starting from the I/O number specified by "n", and stores it in the area starting from the device specified by The following 6 modules (Q series only) support the instruction. •...
Page 626 TYPERD, TYPERDP • When the target module occupies two slots The start I/O number to be specified may differ from that of the target module. For the start I/O number, refer to the manual of each module. Example QJ71GP21S-SX • Specify a value that is the sum of the start I/O number of the mounted module and 0010 Power supply QJ71G P21S-SX Empty Empty Empty Empty Empty Empty...
Page 627 TYPERD, TYPERDP (b) When the model name has not been written to the target module (example: QX40) b8 b7 Stores 1. Indicates that the character string consists of module type and the number of points is stored. Nine words are used. Stores the character string consists of module type and the number of points.
Page 628 TRACE, TRACER Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 2110 The target module cannot be communicated due to a failure. ––...
Page 629 TRACE, TRACER Function The sampling trace is the function that collects the device data of a CPU module consecutively. To execute the sampling trace, turn ON SM801 when SM800 is ON. Trace ends by TRACE TRACER number of trace Trace start request Trigger condition enabled after trigger Trace reset Number of trace...
Page 630 SP.FWRITE Program Example (1) The following program executes the TRACE instruction when X0 is turned ON, and resets the TRACE instruction with the TRACER instruction when X1 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 7.18.12 SP.FWRITE Writing data to designated file Ver.
Page 631 SP.FWRITE Operation Error Setting Setting Meaning Set by Data Type Data Range Dummy –– –– Drive designation User Head number of the devices storing the control data. The following control data is required. Device Item Contents/Setting Data Setting Range Set by Designate the execution type.
Page 632 SP.FWRITE Setting Setting Meaning Set by Data Type Data Range Head number of the devices storing the data. Written data is expressed as follows: Device Item Contents/Setting Data Setting Range Set by Designate the number of data to request writing (word units). 1 to 480 No.
Page 633 SP.FWRITE (3) Be sure to use in units of words to designate the No. of request write data ( ) and the file position ( +4 and +5). The following shows the method for writing binary data when No. of request write data and file position are specified. Control data H0000 Execution/completion type...
Page 634 SP.FWRITE (c) When the designated file does not exist, a new file is created and the data is saved from the beginning of the file. The attributes of this new file are set using the archive attributes. (d) An error occurs when the saving space becomes full while data is added and saved. In such a case, the data that is successfully added/saved remains in the medium.
Page 635 SP.FWRITE When data is written after CSV format conversion and the designated number of columns is other than "0", the data is stored as table data with designated number of columns in a CSV format file. Example When data is written after CSV format conversion and the designated No. of columns is other than "0": SP.FWRITE D20 D99 M0 * Designation in word units...
Page 636 SP.FWRITE (g) When data is added by the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/ LCPU of which the first 5 digits of the serial number are 01112 or higher: [Specify the file to which data will be written.] (If a file exists, delete it and create a new file again.) Execution type = CSV format File position...
Page 637 SP.FWRITE Below is the method for calculating the file size (total number of bytes) when a CSV format file is written to the ATA card. Total number of bytes = Total bytes excluding final line + bytes of final line (Number of bytes on a line = number of columns + 1 + total bytes of all data values on line For all lines but the final line, this is the specified number of columns.
Page 638 SP.FWRITE Program Example (1) When X10 is turned ON, the following program adds four bytes of bina ata (00 , 01 , 02 , and 03 ) to file RY D "ABCD.BIN" in the memory card inserted to drive 2. •...
Page 639 SP.FWRITE (2) When X10 is turned ON, the following program creates a file named "ABCD.CSV" in the memory card inserted to drive 2, and writes four bytes of data (00 , 01 , 02 , and 03 ) as two-column table data in CSV format. •...
Page 640 SP.FREAD 7.18.13 SP.FREAD Reading data from designated file Ver. High Basic Process Redundant Universal LCPU performance 7.18.13 SP.FREAD • Universal model QCPU: Models other than Q00UJCPU, Q00UCPU, and Q01UCPU Command SP.FREAD SP.FREAD Setting Internal Devices Constants R, ZR Other Data Word Word K, H...
Page 641 SP.FREAD Setting Setting Meaning Set by Data Type Data Range Designate the file position to start reading when binary data reading is designated by 00000000 : Starting at the beginning of the file 00000001 to FFFFFFFE : From the designated position (The unit for the value is determined by word/byte unit designation.) FFFFFFFF...
Page 642 SP.FREAD Setting Setting Meaning Set by Data Type Data Range Bit device that turned ON at the completion of the processing. +1 is also turned ON at error completion.) Device Item Contents/Setting Data Setting Range Set by Indicates the completion of the processing. Completion ON: Completed ––...
Page 643 SP.FREAD (3) Be sure to use word units to designate the number of request read data ( +2), file position ( +4 and +5), and reading result (No. of read data) ( The following shows how the data is read in binary data reading operation. Control data H0000 Execution/completion type...
Page 644 SP.FREAD (e) When the designated number of columns is 0, the data is read by ignoring the rows in CSV format file. Example When data is read after CSV format conversion and the designated No. of columns is 0: Data created by EXCEL Measured value Main / sub item Length...
Page 645 SP.FREAD If the number of columns varies in each row, the data is also read by ignoring the rows. Such file cannot be created using EXCEL. This happens when CSV file is modified by a user. Example If the number of columns varies in each row when the data is read: Main / sub item , , Measured value Excess CR LF...
Page 646 SP.FREAD When data is read after CSV format conversion and the designated number of columns is other than 0, the data is read as the table with designated number of columns in CSV format file. The elements outside of the designated columns are ignored.
Page 647 SP.FREAD If the number of columns varies in each row, the elements outside of the designated columns are ignored and "0" is added to the places where elements do not exist. Example If the number of columns varies in each row when the data is read: Main / sub item , , Measured value Excess CR LF...
Page 648 SP.FREAD (g) With the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU whose first 5 digits of the serial number are "01112" or later, it is possible to divide read operation into multiple times. [Specify the row desired to start read.] Execution type = CSV format Starting row number...
Page 649 SP.FREAD (h) When data is read after CSV format conversion, the numerical values that are out of range or the elements other than numerical values in the object CSV format file are converted into 0 When data is read after CSV format conversion, numerical values are read and converted as follows: Numerical Values in CSV -32768 to -1 0 to 32767...
Page 650 SP.FREAD Program Example (1) The following program reads 4 bytes of binary data from the beginning of file "ABCD.BIN" in the memory card inserted to drive 2 when X10 is turned ON. • Assume that 8 points from (D0) are reserved for the control data devices. •...
Page 651 SP.DEVST (2) The following program reads file "ABCD.CSV" in the memory card inserted to drive 2 as two-column table data in CSV format when X10 is turned ON. • Assume that 8 points from (D0) are reserved for the control data devices. •...
Page 652 SP.DEVST Function (1) Writes device data for the number of points specified at n2 of the device to the write offset, which is specified for n1, of the device data storage file in the standard ROM. n1 is the offset from the head of device data storage file and specified by word offset (in units of 16-bit words). Standard ROM Device data Write offset n1...
Page 653 S.DEVLD, SP.DEVLD Program Example (1) The program which writes the ten points of data from D100 to the device data storage file in the standard ROM when M0 turns ON. [Ladder Mode] [List Mode] Step Instruction Device Caution (1) The value written to the standard ROM is the value at execution of this instruction. (2) The standard ROM write count index (SD687 and SD688) is increased by the execution of the SP.DEVST instruction.
Page 654 PLOADP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 2410 The device data storage file is not set at "PLC file" of PLC parameter. ––...
Page 655 PLOADP (a) When the program Nos. have been set consecutively, the new program is added at the end of the preset program Nos. When programs No. 1 to 5 have been set, the new program is added as program No. 6. Program No.
Page 656 PUNLOADP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 2401 The file size of the local devices cannot be reserved. ––...
Page 657 PUNLOADP Function (1) The standby program stored in the program memory (drive 0) is deleted from the program memory. (The program set as the "scan execution type" with the PSCAN instruction or the program set as the "low speed execution type" with the PLOW instruction cannot be deleted.) (2) The program No.
Page 658 PSWAPP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 2410 –– –– ––...
Page 659 PSWAPP (2) The program to be transferred to the program memory by the PSWAPP instruction will have the program No. of the program to be deleted from the program memory. (If there is an open program No. before the program to be deleted from the program memory, the program to be transferred to the program memory will not have the open program No.) When program No.
Page 660 RBMOV, RBMOVP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code 2410 –– ––...
Page 661 RBMOV, RBMOVP (2) The transfer is available even if there is an overlap between the source and destination devices. For the transmission to the smaller number of device, the data is transferred from . For the transmission to the larger number of device, the data is transferred from +(n-1).
Page 662 RBMOV, RBMOVP Program Example (1) The following program outputs the lower four bits of data in R66 to R69 to Y30 through Y3F in units of 4 points. [Ladder Mode] [List Mode] Step Instruction Device Before execution After execution (source of transfer) (destination of transfer) 1 1 0 1 Y33 to Y30...
Page 663 RBMOV, RBMOVP The RBMOV (P) instruction is useful to batch transfer a large quantity of file register data with the QnHCPU/QnPHCPU/ QnPRHCPU. For the QnUCPU, the processing speed of the RBMOV instruction is equivalent to that of the BMOV instruction. The comparison of processing speed between the RBMOV and BMOV instructions is as follows: Transfer from file registers to internal devices/internal devices to file registers Target memory...
Page 664 UMSG Transfer from file registers to file registers Target memory 1 word 1000 words 10000 words Instruction where file register Min. Max. Min. Max. Min. Max. is stored Standard RAM 20.0 µs 91.0 µs 775.0 µs QnHCPU RBMOV SRAM card 22.5 µs 545.0 µs 5300.0 µs...
Page 665 UMSG Function (1) The string data specified by is displayed as a user message in the display unit. The string specified directly by (surrounded by double quotation marks (")) or the string from the device number specified by until the device number storing "00 "...
Page 666 UMSG Program Example (1) This program displays the string stored after D10 on the display unit, when X10 is set to "on". [Ladder Mode] [List Mode] Step Instruction Device [Action] b15 to b8 b7 to b0 User message Line-A Working Run UMSG instruction (2) This program displays "Line-A Working"...
Page 667 S.ZCOM, SP.ZCOM CHAPTER 8 INSTRUCTIONS FOR DATA LINK Network refresh instructions Remark In this chapter, instruction names are abbreviated as follows if not specified particularly. • S(P).ZCOM ZCOM • S(P).RTWRITE RTWRITE • S(P).RTREAD RTREAD 8.1.1 S.ZCOM, SP.ZCOM Refresh for the designated module 8.1.1 S.ZCOM, SP.ZCOM High...
Page 668 S.ZCOM, SP.ZCOM (2) The ZCOM instruction does not perform the following processing. (a) Communication processing between CPU module and programming tool (b) Monitor processing of other station (c) Read processing of buffer memory of other intelligent function module by serial communication module. (d) Low-speed cyclic data transmission of MELSECNET/H (3) CC-Link IE Controller Network and MELSECNET/H (PLC to PLC network) (a) When the scan time for the sequence program of host station is longer than the scan time for the other station, the...
Page 669 S.ZCOM, SP.ZCOM (4) MELSECNET/H (remote I/O network) The link refresh of the remote master station is performed by the "END processing" of the CPU module. Since link scan is performed at completion of link refresh, link scan 'synchronizes' with the program of the CPU module. When the ZCOM instruction is used at the remote master station, link refresh is performed at the point of ZCOM instruction execution, and link scan is performed at completion of link refresh.
Page 670 S.ZCOM, SP.ZCOM Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The module specified with the head I/O number is not a network 2111 ––...
Page 671 S.RTREAD, SP.RTREAD Reading/Writing Routing Information 8.2.1 S.RTREAD, SP.RTREADReading routing information Ver. 8.2.1 High Basic Process Redundant Universal LCPU S.RTREAD, SP.RTREAD performance • LCPU: The serial number (first five digits) is "13012" or later. Command S.RTREAD S.RTREAD Command SP.RTREAD SP.RTREAD : Transfer destination network No. (1 to 239) (BIN 16 bits) : Head number of the devices that stores the read data (Device name) Setting Internal Devices...
Page 672 S.RTWRITE, SP.RTWRITE Program Example (1) The following program reads the routing information for the network number specified by D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] [Content of routing parameter setting] Transfer Relay network Relay station destination number...
Page 673 S.RTWRITE, SP.RTWRITE Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code The value in n is the value other than 1 to 239. The data of or later exceeds each setting range.
Page 674 CHAPTER 9 MULTIPLE CPU DEDICATED INSTRUCTION Writing to the CPU Shared Memory of Host CPU The S.TO or TO instruction is used to write to the CPU shared memory of the host station in the multiple CPU system. The following table indicates the usability of the S.TO and TO instructions. CPU Module S.TO Instruction TO Instruction...
Page 675 S.TO, SP.TO The following figure shows the processing performed when the TO instruction is executed in CPU No. 1. Intelligent CPU No. 1 CPU No. 2 function module Device Device Buffer Data shared shared memory memory memory write memory memory Writes data [ TO H3E0 n2 n3 ]...
Page 676 S.TO, SP.TO Function (1) Writes device data of words n3 to n4 to the CPU shared memory address specified by n2 of the host CPU module or later address. When writing is completed, the completion bit specified by turns ON. Host CPU CPU shared memory Device memory...
Page 677 S.TO, SP.TO Writing data to CPU shared memory can be performed using the intelligent function module device. For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals). Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Page 678 TO, TOP, DTO, DTOP Remark The n1 is specified by the first 3 digits of the hexadecimal 4 digits which represent the head I/O number of the slot mounted to the CPU module. CPU Slot Slot 0 Slot 1 Slot 2 Head I/O number 3E00 3E10...
Page 679 TO, TOP, DTO, DTOP When a constant is specified to , writes the same data (value specified to ) to the area of n3 words from the specified CPU shared memory. CPU shared memory of host CPU (n1) Constant (When "5" is designated Writes the n3 words same data to...
Page 680 TO, TOP, DTO, DTOP (1) Writes device data of words to (n3×2) to the CPU shared memory address specified by n2 of the host CPU module or later address. Host CPU CPU shared memory Device memory of host CPU (n1) n3 2 Writes the data of (n3 2)
Page 681 TO, TOP, DTO, DTOP Program Example (1) The following program stores 10 points of data from D0 into address 10000 of the CPU shared memory of CPU No. 1 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device (2) The following program stores 20 points of data from D0 into address 10000 of the CPU shared memory of CPU No.
Page 682 Reading from the CPU Shared Memory of another CPU The FROM(P)/DFRO(P) instruction of Multiple CPU system can be read from the following memories. • Buffer memory of intelligent function module • CPU shared memory of other CPU module • CPU shared memory of host CPU module (applicable for the Basic model QCPU and Universal model QCPU) The following figure shows the processing performed when the FROM(P) instruction is executed in CPU No.
Page 683 FROM, FROMP, DFRO, DFROP 9.2.1 FROM, FROMP, DFRO, Reading from other CPU shared memory DFROP Ver. Ver. High Basic Process LCPU Redundant Universal performance • Q00CPU, Q01CPU: The serial number (first five digits) is 9.2.1 FROM, FROMP, DFRO, DFROP "04122" or later. •...
Page 684 FROM, FROMP, DFRO, DFROP (b) CPU shared memory address of the Universal model QCPU CPU shared memory address Host CPU operation information area 512(200 System area 2048(800 Host CPU refresh area User free area 4096(1000 Read designation Unusable permitted area 10000(2710 Multiple CPU high speed transmisson area...
Page 685 FROM, FROMP, DFRO, DFROP Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code No CPU module is installed at the position specified for the head I/O 2110 ––...
Page 686 FROM, FROMP, DFRO, DFROP When High Performance model QCPU, Process CPU is used Command FROM FROM Command FROMP FROMP : Head I/O number of the reading target CPU module (BIN 16 bits) : Head address of data to be read (BIN 16 bits) : Head number of the devices where the read data is stored (BIN 16 bits) : Number of read data (BIN 16 bits) Internal Devices...
Page 687 FROM, FROMP, DFRO, DFROP Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code No CPU module is installed at the position specified for the head I/O 2110 ––...
Page 688 CHAPTER 10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS 10.1 Overview The multiple CPU high-speed transmission dedicated instruction directs the Universal model QCPU to write/read device data to/from the Universal model QCPU in another CPU. The following shows an operation when CPU No.1 writes device data to CPU No.2 with the multiple CPU high-speed transmission dedicated instruction.
Page 689 Writable/readable devices (a) Writable/readable device names The following table shows the devices that can be written to/read from the Univesal model QCPU in another CPU with the multiple CPU high-speed transmission dedicated instruction. Setting of target Category Type Device name Remarks device Requirements for the setting...
Page 690 (b) String specification The string specification is a method to specify a device in another CPU to be written/read by character string. Program for string specification with the DP.DDWR instruction DP.DDWR H3E1 D100 "D200" Specifies "D200", a device in another CPU to be written by characer string.
Page 691 (b) The following shows configuration of the multiple CPU high speed transmission area when the multiple CPU system is configured with three CPU modules and the system area size is 1k word. Multiple CPU high speed Multiple CPU high speed Multiple CPU high speed transmission area in transmission area in...
Page 692 (7) Interlock when using the multiple CPU high-speed transmission dedicated instruction (a) Special relays SM796 to SM799 (maximum number of used blocks for multiple CPU high-speed transmission dedicated instruction setting) can be used as an interlock for the multiple CPU high-speed transmission dedicated instruction.
Page 693 (b) Program example when SM796 to SM799 are used as an interlock The following shows a program that executes the D.DDWR instruction to CPU No.2 at the rise of X0, and executes the D.DDWR instruction to CPU No.3 at the rise of X1. The maximum number of used blocks for multiple CPU high-speed transmission dedicated instruction SM402 SD797...
Page 694 (8) Program example when the multiple CPU high-speed transmission dedicated instructions are executed to CPU modules by turns When the multiple CPU high-speed transmission dedicated instructions are executed to Universal model QCPUs by turns, release an interlock to prevent the concurrent execution. Use the cyclic transmission area device (from U3En\G10000) as an interlock.
Page 695 Program example when the multiple CPU high-speed transmission dedicated instruction is executed at CPU No.2 SM402 SD796 Turn-on for one Maximum number of used blocks scan after RUN (CPU No.1) Read instruction During execution the DDRD instruction U3E1\G10000.0 is turned on while CPU No.2 is executing the DP.DDRD instruction. U3E0\G10000.0 SM796 U3E1\...
Page 696 (a) Program example when one D(P).DDWR instruction is executed. The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction. In the following program example, the next D.DDWR instruction is executed after the completion device of the D.DDWR instruction (M2) turns on so that only one D.DDWR instruction may be executed.
Page 697 (b) Program example when the D(P).DDWR instructions are executed concurrently The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction. As shown on the program example, multiple CPU device write/read instructions can be executed concurrently. When reading/writing devices with the multiple CPU high-speed transmission dedicated instructions concurrently, the more the total number of blocks in the multiple CPU high speed transmission area (send area), the more the time taken to complete reading/writing with the multiple CPU high-speed transmission dedicated instruction can be...
Page 698 D.DDWR, DP.DDWR 10.2 D.DDWR, DP.DDWR Writing Devices to Another CPU Ver. High Basic Process Redundant Universal LCPU performance • Universal model QCPU: The serial number (first five digits) is "10012" or later. 10.2 D.DDWR, DP.DDWR • Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU cannot be used.
Page 699 D.DDWR, DP.DDWR Function (1) In multiple CPU system, data stored in a device specified by host CPU ( ) or later is stored by the number of write points specified by ( +1) into a device specified by another CPU (n) ( ) or later.
Page 700 D.DDWR, DP.DDWR Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code Specified another CPU is incorrect. Or the multiple CPU high-speed transmission dedicated instruction is disabled.
Page 701 D.DDRD, DP.DDRD Caution (1) Digit specification of bit device is possible for n, , and . Note that when the digit specification of bit device is made to , the following conditions must be met. • Digits are specified by 16 bits (4 digits). •...
Page 702 D.DDRD, DP.DDRD Control Data Device Item Setting data Setting range Set by An execution result upon completion of the instruction is stored. Completion status –– System 0000( ): No errors (normal completion) Other than 0000( ): Error code (error completion) Number of read Set the number of read points in units of words.
Page 703 D.DDRD, DP.DDRD Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. Q00J/ Error Error details Q00/ QnPH QnPRH LCPU code Specified another CPU is incorrect. Or the multiple CPU high-speed transmission dedicated instruction is disabled.
Page 704 D.DDRD, DP.DDRD Program Example (1) This program stores data by 10 words starting from D0 in CPU No.2 into W10 or later in host CPU when X0 turns on. [Ladder Mode] [List Mode] Caution (1) Digit specification of bit device is possible for n, , and .
Page 705 SP.CONTSW CHAPTER 11 REDUNDANT SYSTEM INSTRUCTIONS (For REDUNDANT CPU) 11.1 SP.CONTSW System Switching 11.1 SP.CONTSW High Basic Process LCPU Redundant Universal performance Command SP.CONTSW SP.CONTSW : Value other than 0 and used to identify the processing that issued the system switching request (BIN 16 bits) : Error completion device number (bits) Setting Internal Devices...
Page 706 SP.CONTSW (b) If systems could not be switched due to any of the reasons given in the following table, the error completion device turns ON when system switching is executed in the END processing. Reason No. Reasons for System Switching Failure Normally completed Tracking cable is disconnected or faulty.
Page 707 SP.CONTSW Program Example (1) The following program executes system switching on the leading edge of the system switching command (M100). If the system switching command (M100) remains ON, the SP.CONTSW instruction is also executed by the new control system CPU module after system switching. Therefore, M101 is added to the execution conditions as a consecutive switching prevention flag.
Page 708 APPENDICES Appendix 1 OPERATION PROCESSING TIME Appendix 1.1 Definition (1) Processing time taken by the QCPU, LCPU is the total of the following processing times. • Total of each instruction processing time • END processing time (including I/O refresh time) •...
Page 709 Appendix 1.2 Operation Processing Time of Basic Model QCPU The processing time for the individual instructions are shown in the table on the following pages. Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time rather than as being strictly accurate.
Page 710 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU When not executed 0.88 0.55 After time up 0.88 0.55 When 0.88 0.55 executed When added 0.96 0.60 When not executed 0.88 0.55 After time up 0.88 0.55 When 0.88 0.55 executed When added 0.96...
Page 711 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU When not executed 0.50 0.34 0.25 SFTP When executed 0.40 0.32 0.20 D0.0 –– 0.20 0.16 0.10 Error check performed No error check performed FEND (• Battery check) (• Fuse blown check) (•...
Page 712 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU When not executed 0.70 0.56 0.35 AND < In conductive status 0.80 0.64 0.40 When executed In non-conductive status 0.80 0.64 0.40 When not executed 0.70 0.56 0.35 OR < In conductive status 0.80 0.64 0.40...
Page 713 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU When not executed 0.80 0.64 0.40 ANDD > = In conductive status 0.80 0.50 When executed In non-conductive status 0.80 0.50 When not executed 0.80 0.64 0.40 ORD > = In conductive status 0.80 0.50 When executed...
Page 714 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU –– B - P S1 S2 D –– B - P S1 S2 D –– DB+P S1 S2 D –– DB+P S1 S2 D DB - –– DB - P DB - S1 S2 D ––...
Page 715 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU DGBIN –– DGBINP –– NEGP DNEG –– DNEGP n = 1 BKBCD n = 96 BKBCDP n = 1 BKBIN n = 96 BKBINP 0.70 0.56 0.35 = D0, = D1 MOVP = D0, = J1 \ W1...
Page 716 (3) Application instructions The processing time when the instruction is not executed is calculated as follows: Q00JCPU ····················································· 0.20 (No. of steps for each instruction + 1) µs Q00CPU ······················································· 0.16 (No. of steps for each instruction + 1) µs Q01CPU ·······················································...
Page 717 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU n = 1 n = 15 RCRP n = 1 n = 15 ROLP n = 1 n = 15 RCLP n = 1 DROR n = 31 DRORP n = 1 DRCR n = 31 DRCRP...
Page 718 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU DSUM DSUMP = FFFFFFFF n = 2 DECO n = 8 DECOP M1 = ON n = 2 ENCO M4 = ON M1 = ON ENCOP n = 8 M256 = ON ––...
Page 719 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU FCALL Pn –– FCALLP Pn FCALL Pn –– FCALLP Pn –– –– IXEND –– Number of contacts 1 IXDEV + IXSET Number of contacts 14 FIFW Number of data points 0 FIFWP Number of data points 96 FIFR...
Page 720 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU HOUR –– HOURP –– WDTP DUTY –– ZRRDB –– –– ZRRDBP ZRWRB –– –– ZRWRBP ADRSET –– ADRSETP ZPUSH –– ZPUSHP ZPOP –– ZPOPP ZCOM –– (4) Processing time for QCPU instructions (QCPU instructions only) Processing Time (µs) Instruction Condition (Device)
Page 721 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU When not executed ORE < = Single precision When In conductive status 45.0 37.5 34.5 executed In non-conductive status 37.5 31.5 28.5 In conductive status 45.5 37.5 35.0 LDE < Single precision In non-conductive status 46.5 38.5...
Page 722 Processing Time (µs) Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU Single precision 204.0 173.0 157.0 SINP Single precision 187.0 158.0 144.0 COSP Single precision 224.0 190.0 173.0 TANP Single precision 51.0 43.0 39.0 RADP Single precision 51.0 43.0 39.0 DEGP Single precision 60.0 51.0 46.5...
Page 723 Instruction Processing Time (µs) Condition/Number of Points Processed Name Q00JCPU Q00CPU Q01CPU With auto refresh of CPU Refresh range: 2k words –– shared memory (0.5k words assigned equally to all CPUs) Without auto refresh of –– –– CPU shared memory Read from CPU shared n3 = 1 ––...
Page 724 Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU The processing time for the individual instructions are shown in the table on the following pages. Operation processing time can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing times rather than as being strictly accurate.
Page 725 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH When not executed 0.63 0.27 0.27 0.27 After time up 0.63 0.27 0.27 0.27 OUTH When 0.63 0.27 0.27 0.27 executed When added 0.63 0.27 0.27 0.27 When not executed 0.158 0.068 0.068 0.068 0.158...
Page 726 (2) Basic instructions The processing time when the instruction is not executed is calculated as follows: Q02CPU ······················································· 0.079 (No. of steps for each instruction + 1) µs Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU, Q12PRHCPU, Q25PRHCPU ················································· 0.034 (No. of steps for each instruction + 1) µs Processing Time (µs) Instruction Condition (Device)
Page 727 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH In conductive status 0.55 0.24 0.24 0.24 LDD = In non-conductive status 0.39 0.17 0.17 0.17 When not executed 0.39 0.17 0.17 0.17 ANDD = In conductive status 0.55 0.24 0.24 0.24 When executed In non-conductive status 0.39...
Page 728 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH In conductive status Single 14.9 precision In non-conductive status 14.9 LDE = In conductive status –– –– Double 14.9 precision In non-conductive status –– –– 14.9 When not executed 0.55 0.24 0.24 0.24 Single In conductive status...
Page 729 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH When not executed 0.55 0.24 0.24 0.24 Single In conductive status When 14.9 precision executed In non-conductive status 14.9 ORE<> When not executed 0.55 0.24 –– –– In conductive status –– –– Double 14.9 When...
Page 730 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH When not executed 0.55 0.24 0.24 0.24 In conductive status Single 14.9 When precision executed In non-conductive status 14.9 ANDE<= When not executed 0.55 0.24 –– –– Double In conductive status –– ––...
Page 731 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH In conductive status Single 14.9 precision In non-conductive status 14.9 LDE>= In conductive status –– –– 14.9 Double precision In non-conductive status –– –– 14.9 When not executed 0.55 0.24 0.24 0.24 In conductive status Single 14.9...
Page 732 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH When not executed 0.56 0.23 0.23 0.23 AND$ > In conductive status When executed In non-conductive status When not executed 0.56 0.24 0.24 0.24 OR$ > In conductive status When executed In non-conductive status In conductive status LD$ <...
Page 733 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH When executed 0.71 0.31 0.31 0.31 S1 S2 D When executed 0.79 0.34 0.34 0.34 S1 S2 D When executed 0.71 0.30 0.30 0.30 D - P S1 S2 D When executed 0.79 0.34 0.34...
Page 734 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH 0.78 0.78 0.78 Single = 0, precision 0.78 0.78 0.78 –– –– Double = 0, precision –– –– = 0, Single precision S1 S2 D –– –– Double = 0, S1 S2 D precision ––...
Page 735 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH Single precision = 32766.5 INTP –– –– Double precision –– –– = 32766.5 Single precision DINT = 1234567890.3 DINTP –– –– Double precision –– –– = 1234567890.3 0.92 0.92 0.92 Single precision 0.92 0.92 0.92...
Page 736 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH EMOV –– 0.63 0.27 0.27 0.27 EMOVP $MOV –– $MOVP –– 0.40 0.17 0.17 0.17 CMLP DCML –– 0.55 0.24 0.24 0.24 DCMLP n = 1 BMOV n = 96 BMOVP n = 1 FMOV n = 96 FMOVP...
Page 737 (3) Application instructions The processing time when the instruction is not executed is calculated as follows: Q02CPU ························································ 0.079 (No. of steps for each instruction + 1) µs Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU, Q12PRHCPU, Q25PRHCPU ················································· 0.034 (No. of steps for each instruction + 1) µs Processing Time ( µs) Instruction Condition (Device)
Page 738 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH n = 1 0.68 0.68 0.68 n = 15 0.68 0.68 0.68 RCRP n = 1 0.85 0.85 0.85 n = 15 0.85 0.85 0.85 ROLP n = 1 0.68 0.68 0.68 n = 15 0.68 0.68...
Page 739 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH SUMP = FFFF DSUM DSUMP = FFFFFFFF n = 2 DECO n = 8 DECOP M1 = ON n = 2 M4 = ON ENCO M1 = ON ENCOP n = 8 M256 = ON ––...
Page 740 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH CALL Pn –– CALLP Pn Return to original program Return to other program Internal file pointer FCALL Pn FCALLP Pn Common pointer FCALL Pn –– FCALLP Pn ECALL * Pn ECALLP * Pn ––...
Page 741 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH –– –– –– –– n3 = 1 –– –– –– –– TO n1 n2 –– –– –– –– TOP n1 n2 n3 = 1000 –– –– –– –– –– –– –– –– n3 = 1 ––...
Page 742 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH BCDDA BCDDAP = 9999 DBCDDA DBCDDAP = 99999999 DABIN DABINP = - 32768 DDABIN DDABINP = - 2147483648 HABIN HABINP = FFFF DHABIN DHABINP = FFFFFFFF DABCD DABCDP = 9999 DDABCD DDABCDP = 99999999 COMRD ––...
Page 743 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH EMOD –– EMODP EREXP –– 1656 EREXPP Single precision SINP Double precision 1945 –– –– Single precision COSP Double precision 2618 1127 –– –– Single precision TANP Double precision 2618 1127 –– ––...
Page 744 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH DLIMIT –– DLIMITP BAND –– BANDP DBAND –– DBANDP ZONE –– ZONEP DZONE –– DZONEP RSET –– RSETP QDRSET –– QDRSETP QCDSET –– QCDSETP DATERD –– DATERDP DATEWR –– DATEWRP DATE+ No digit increase DATE+P Digit increase DATE -...
Page 745 Processing Time (µs) Instruction Condition (Device) QnPH QnPRH ZCOM –– READ –– –– –– –– –– SREAD –– –– –– –– –– WRITE –– –– –– –– –– SWRITE –– –– –– –– –– SEND –– –– –– –– –– RECV ––...
Page 746 (b) Instructions available from function version B Processing Time (µs) Instruction Condition/Number of Points Processed QnPH QnPRH Refresh range: 2k words (0.5k words –– assigned equally to all CPUs) With auto refresh of CPU shared memory Refresh range: 4k words (1k words assigned equally to all ––...
Page 747 (6) Table of the time to be added when file register, module access device or link direct device is used Device Specification Processing Time (µs) Instruction Data Location QnPH QnPRH Source 5.56 2.40 2.40 2.40 Destination 4.44 1.91 1.91 1.91 When standard Source 2.60...
Page 748 Appendix 1.4 Operation Processing Time of Universal Model QCPU The processing time for the individual instructions are shown in the table on the following pages. Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time rather than as being strictly accurate.
Page 749 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. In conductive status LD<> 0.360 0.240 0.180 0.120 In non-conductive status When not executed In conductive status AND<> 0.360 0.240 0.180 0.120 When executed In non-conductive status...
Page 750 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed ORD<> When In conductive status 0.360 0.240 0.180 0.120 executed In non-conductive status In conductive status LDD> 0.360 0.240 0.180 0.120...
Page 751 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When executed 3.700 12.100 3.700 12.100 3.700 12.100 4.000 8.200 S1 S2 D When executed 4.000 14.000 4.000 14.000 4.000 14.000 4.200 12.400 S1 S2 D...
Page 752 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. –– 3.500 10.100 3.500 10.100 3.500 10.100 1.900 10.100 Basic –– 3.500 10.100 3.500 10.100 3.500 10.100 1.900 10.100 instruction –– 3.500 10.100 3.500...
Page 753 Remark For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON execution instruction. Example MOVP instruction, WANDP instruction etc. (b) When using Q03UD(E)HCPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, and Q100UDEHCPU Processing Time (µs) Q04/Q06UD(E)H...
Page 754 Processing Time (µs) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH Category Instruction Condition (Device) Q03UD(E)CPU Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed OR> In conductive status When 0.060 0.0285 0.0285 0.0285 executed In non-conductive status In conductive status LD<= 0.060 0.0285 0.0285...
Page 755 Processing Time (µs) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH Category Instruction Condition (Device) Q03UD(E)CPU Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed ANDD<= In conductive status When 0.060 0.0285 0.0285 0.0285 executed In non-conductive status When not executed ORD<= In conductive status When 0.060...
Page 756 Processing Time (µs) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH Category Instruction Condition (Device) Q03UD(E)CPU Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. 0.120 0.057 0.057 0.057 = 0, Single S1 S2 D precision 0.120 0.057 0.057 0.057 Single 4.500 5.600 3.900 4.900 0.285 0.285 S1 S2 D...
Page 757 Processing Time (µs) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH Category Instruction Condition (Device) Q03UD(E)CPU Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. When executed 0.060 0.0285 0.0285 0.0285 WAND When executed 0.080 0.038 0.038 0.038 WAND S1 S2 D When executed 0.060 0.0285 0.0285 0.0285...
Page 758 Remark For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON execution instruction. Example MOVP instruction, WANDP instruction etc. (2) Table of the time to be added when file register, extended data register, extended link register, and module access device are used (a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU Device...
Page 759 (b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UDE(H)CPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU and Q100UDEHCPU Device Processing Time (µs) Device name Data Specification Q03UD(E) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH Location Q26UD(E)HCPU Source 0.100 0.048 0.048 0.048 Destination 0.100 0.038 0.038 0.038 Source 0.100 0.048 0.048 0.048 When standard...
Page 760 (3) Table of the time to be added when F/T(ST)/C device is used in OUT/SET/RST instruction (a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU Instruction Processing Time (µs) Device name Condition name Q00UJCPU Q00UCPU Q01UCPU Q02UCPU When not executed 2.900 2.900 2.900 2.100...
Page 761 Appendix 1.4.2 Processing time of instructions other than subset instruction The following table shows the processing time of instructions other than subset instructions. • The processing time shown in "(1) Table of the processing time of instructions other than subset instructions" applies when the device used in an instruction does not meet the device condition for subset processing (For device condition that does not trigger subset processing, refer to Page 102, Section 3.5.1).
Page 762 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.100 LDE= precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700...
Page 763 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.360 0.240 0.180 0.120 Double ORED= In conductive status When 4.700 33.200 4.700 33.200 4.700 33.200 4.100 23.800 precision executed In non-conductive status...
Page 764 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. In conductive status 8.300 39.300 8.300 39.300 8.300 39.300 5.600 15.200 LD$< > In non-conductive status 8.300 39.300 8.300 39.300 8.300 39.300 5.600 15.400...
Page 765 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. n = 1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 22.600 BKCMP = S1 S2 D n = 96 64.500 85.500 64.500 85.500 64.500...
Page 766 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. –– 15.400 64.300 15.400 64.300 15.400 64.300 14.400 34.000 –– 19.700 71.000 19.700 71.000 19.700 71.000 9.200 22.900 S1 S2 D 3.100 19.600 3.100...
Page 767 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. PLSY –– 6.400 7.100 6.400 7.100 6.400 7.100 3.500 4.700 Basic –– 3.900 4.600 3.900 4.600 3.900 4.600 3.400 3.400 instruction ––...
Page 768 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. n = 1 6.600 14.900 6.600 14.900 6.600 14.900 5.000 6.500 WTOB n = 96 37.700 46.100 37.700 46.100 37.700 46.100 36.000 38.400 n = 1...
Page 769 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When selecting I/O refresh only 18.100 89.100 18.100 89.100 18.100 89.100 12.800 79.000 When selecting CC-Link refresh 33.300 132.000 33.300 132.000 33.300 132.000 24.900 119.000 only (master station side)
Page 770 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. No display no display 1.500 7.100 1.500 7.100 1.500 7.100 5.100 5.100 LEDR LED instruction execution 38.900 109.000 38.900 109.000 38.900 109.000 35.700 89.200 no display...
Page 771 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. MIDR –– 11.700 30.600 11.700 30.600 11.700 30.600 9.500 19.100 MIDW –– 12.400 24.000 12.400 24.000 12.400 24.000 10.300 18.200 No match 22.000 38.200 22.000...
Page 772 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. = 12.3 E + 5 Single 12.200 22.100 12.200 22.100 12.200 22.100 8.950 19.500 S1 S2 D precision = 3.45 E + 0 = 12.3 E + 5 Double POWD...
Page 773 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Standard RAM 6.800 26.900 6.800 26.900 6.800 26.900 3.000 16.400 RSET SRAM card –– –– –– –– –– –– 3.000 16.400 SRAM card to standard RAM ––...
Page 774 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.480 0.320 0.240 0.160 In conductive Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400 status of specified In non-conductive date 8.200...
Page 775 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.480 0.320 0.240 0.160 In conductive Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400 status of specified In non-conductive date 8.200...
Page 776 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.480 0.320 0.240 0.160 In conductive Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400 status of specified In non-conductive date 8.200...
Page 777 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.480 0.320 0.240 0.160 In conductive Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000 status of specified In non-conductive clock 8.200...
Page 778 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.480 0.320 0.240 0.160 In conductive Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000 status of specified In non-conductive clock 8.200...
Page 779 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.480 0.320 0.240 0.160 In conductive Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000 status of specified In non-conductive clock 8.200...
Page 780 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When mounting CC-Link 29.400 91.700 29.400 91.700 29.400 91.700 20.600 55.000 module (master station side) When mounting CC-Link 29.500 91.600 29.500 91.600 29.500 91.600...
Page 781 Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Writing to host n4 = 1 64.600 78.100 64.600 78.100 64.600 78.100 64.600 78.100 CPU shared S.TO n1 n2 n3 n4 n4 = 320 115.000 126.000 115.000 126.000 115.000 126.000 154.000 126.000 memory...
Page 782 (b) When using Q03UD(E)JCPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, and Q100UDEHCPU Processing Time (µs) Instruc- Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Condition (Device) tion UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. –– 0.020 0.0095 0.0095 0.0095 When not executed 0.020...
Page 783 Processing Time (µs) Instruc- Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Condition (Device) tion UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.060 0.0285 Single ORE> In conductive status When 3.600 5.100 3.300 4.600 0.0285 0.0285 precision executed In non-conductive status...
Page 784 Processing Time (µs) Instruc- Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Condition (Device) tion UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.060 0.0285 0.0285 0.0285 Double ANDED<= When In conductive status 3.800 7.700 3.300 7.200 3.300 7.200 3.300...
Page 785 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. In conductive status 4.800 8.100 4.500 7.500 4.500 7.500 4.500 7.500 LD$< In non-conductive status 5.000 8.300 4.500 7.900 4.500 7.900...
Page 786 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. ED + 4.800 8.000 4.300 7.200 4.300 7.200 4.300 7.200 Double = 0, precision 1023 1023 4.800 8.000 4.300 7.200 4.300...
Page 787 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. ECON –– 2.600 5.400 2.100 4.500 2.100 4.500 2.100 4.500 EDCON –– 2.800 5.400 2.500 5.400 2.500 5.400 2.500 5.400 EDMOV...
Page 788 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. TEST When executed 4.400 5.300 3.700 4.700 3.700 4.700 3.700 4.700 DTEST When executed 4.500 5.400 3.900 4.800 3.900 4.800 3.900...
Page 789 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. NEXT –– 0.940 1.400 0.770 1.200 0.770 1.200 0.770 1.200 BREAK –– 10.400 5.500 9.100 5.000 9.100 5.000 9.100 5.000 Return to original program...
Page 790 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. When selecting I/O refresh 12.800 29.100 12.400 28.600 12.400 28.600 12.400 28.600 only When selecting CC-Link refresh only (master station 16.000 39.500 15.500...
Page 791 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. FROM n1 n2 n3 = 1 10.800 24.100 10.700 23.600 10.700 23.600 10.700 23.600 n3 = 1000 392.600 413.300 390.900 410.200 390.900 410.200 390.900 410.200 DFRO n1 n2...
Page 792 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. DSTR –– 10.200 12.500 9.600 11.500 9.600 11.500 9.600 11.500 –– 9.800 14.200 8.900 13.000 8.900 13.000 8.900 13.000 DVAL ––...
Page 793 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. = -10 4.000 6.100 3.800 5.500 3.800 5.500 3.800 5.500 Single precision 4.000 6.100 3.800 5.600 3.800 5.600 3.800 5.600 = -10...
Page 794 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. Point No.1 13.200 23.600 12.300 22.500 12.300 22.500 12.300 22.500 < < SM750 Point No.2 = ON Point No.9 13.300 23.600 12.600...
Page 795 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. Standard RAM 3.000 6.300 2.700 5.900 2.700 5.900 2.700 5.900 RSET SRAM card 3.000 6.400 2.600 5.800 2.600 5.800 2.600 5.800...
Page 796 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. Comparison In conductive status 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900 of specified In non-conductive status 7.400 11.600 6.800 10.900...
Page 797 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.008 0.038 0.038 0.038 Comparison In conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800 of specified In non-conductive status...
Page 798 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.008 0.038 0.038 0.038 Comparison In conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800 of specified In non-conductive status...
Page 799 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. When not executed 0.008 0.038 0.038 0.038 Comparison In conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800 of specified In non-conductive status...
Page 800 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. PSTOP –– 82.200 199.000 82.200 199.000 82.200 199.000 82.200 199.000 POFF –– 82.600 198.000 82.600 198.000 82.600 198.000 82.600 198.000 PSCAN ––...
Page 801 Processing Time (µs) Q04/Q06 Q10/Q13/Q20/ Q50/Q100 Category Instruction Condition (Device) UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU Min. Max. Min. Max. Min. Max. Min. Max. Writing to host n4 = 1 34.700 34.900 33.500 34.400 33.500 34.400 33.500 34.400 S.TO CPU shared n4 = 320 85.900 87.600 75.200...
Page 802 (2) Table of the time to be added when file register, extended data register, extended link register, module access device, and link direct device are used (a) When using Q00UJCPU, Q00UCPUI, Q01UCPU and Q02UCPU Device Processing Time (µs) Device name Data Specification Q00UJCPU...
Page 803 (b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU and Q100UDEHCPU Device Processing Time (µs) Device name data Specification Q03UD(E) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH Location Q26UD(E)HCPU Source 0.100 0.048 0.048 0.048 Destination 0.100 0.038 0.038 0.038 When standard Source 0.100 0.048 0.048...
Page 804 Appendix 1.5 Operation Processing Time of LCPU The processing time for the individual instructions are shown in the table on the following pages. Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time rather than as being strictly accurate.
Page 805 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When not executed In conductive status 0.120 0.0285 When executed In non-conductive status In conductive status LD<> 0.120 0.0285 In non-conductive status When not executed AND<>...
Page 806 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When not executed ANDD<> In conductive status 0.120 0.0285 When executed In non-conductive status When not executed ORD<> In conductive status 0.120 0.0285 When executed In non-conductive status In conductive status LDD>...
Page 807 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When executed 3.100 6.800 2.900 4.100 When executed 4.800 8.900 4.200 4.600 S1 S2 D When executed 3.900 7.400 3.400 4.800 S1 S2 D When executed 3.900 8.500 3.700...
Page 808 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. 2.000 3.200 1.750 1.750 SM237=ON n=96 5.600 6.100 3.650 4.150 DFMOV 2.900 4.600 2.250 3.150 Basic SM237=OFF n=96 6.100 8.200 4.200 5.500 instruction –– 2.100 2.900 1.100 2.400...
Page 809 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. –– 1.300 3.200 0.870 2.100 Internal file pointer 2.600 4.000 2.300 3.600 Application CALL Pn Common pointer 4.600 13.500 3.200 4.900 instruction –– 31.200 36.000 26.100 29.300 CALL Pn...
Page 810 Appendix 1.5.2 Processing time of instructions other than subset instruction The following table shows the processing time of instructions other than subset instructions. (1) Table of the processing time of instructions other than subset instructions • The processing time shown in "(1) Table of the processing time of instructions other than subset instructions" applies when the device used in an instruction does not meet the device condition for subset processing (For device condition that does not trigger subset processing, refer to Page 102, Section 3.5.1).
Page 811 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. In conductive status Single 3.900 10.000 0.0285 LDE= precision In non-conductive status 3.900 10.000 0.0285 When not executed 0.120 Single ANDE= In conductive status When 3.400 9.300 0.0285...
Page 812 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When not executed 0.120 0.0285 Double ORED= When In conductive status 4.500 14.900 3.400 9.200 precision executed In non-conductive status 4.500 14.900 3.400 9.200 Double In conductive status 4.800 16.000...
Page 813 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When not executed 0.120 0.0285 AND$< > In conductive status 5.300 16.400 3.900 7.300 When executed In non-conductive status 5.300 16.400 3.900 7.300 When not executed 0.120 0.0285 OR$<...
Page 814 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. n = 1 9.200 15.600 7.500 10.100 BKCMP = S1 S2 D n = 96 60.700 69.100 45.600 50.500 n = 1 9.200 15.600 7.500 10.100 BKCMP<>...
Page 815 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. –– 11.200 24.700 8.100 13.900 –– 7.900 16.600 6.500 10.300 S1 S2 D 2.800 9.400 1.800 4.700 Double FLTD precision = 7FFF 3.300 9.600 2.200 4.800 2.900 9.100...
Page 816 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. RAMP –– 6.700 14.600 5.200 8.400 –– 5.400 14.800 4.900 11.200 Basic PLSY –– 10.500 10.500 7.900 7.900 instruction –– 10.100 10.100 7.500 7.500 –– 14.700 25.100 9.400...
Page 817 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. NDIS When executed 11.200 15.200 11.000 13.200 NUNI When executed 10.600 12.700 7.300 13.200 n = 1 5.400 8.100 4.400 5.800 WTOB n = 96 38.400 40.900 28.200...
Page 818 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When selecting I/O refresh only 8.400 14.600 12.600 17.200 When selecting CC-Link refresh 10.500 29.400 10.100 22.000 only (Master station side) When selecting CC-Link refresh 10.500 29.400 10.100...
Page 819 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. 5.800 10.100 5.600 7.800 DABIN 5.800 10.100 5.600 7.800 = -32768 8.300 12.600 8.100 10.500 DDABIN 8.300 12.600 8.100 10.500 = -2147483648 4.500 8.800 4.400 6.500 HABIN = FFFF...
Page 820 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. SIND Double precision 9.400 22.300 8.500 13.800 COSD Double precision 10.000 22.300 8.800 14.600 TAND Double precision 12.200 24.900 10.800 16.500 ASIND Double precision 12.800 25.900 11.600 16.600...
Page 821 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When not executed 0.160 0.038 Comparison In conductive status 7.300 14.000 6.500 10.700 of specified In non-conductive status 7.300 14.000 6.500 10.700 ANDDT= date Comparison In conductive status 6.100 12.700...
Page 822 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. Comparison In conductive status 7.700 14.200 6.800 10.900 of specified In non-conductive status 7.700 14.200 6.800 10.900 date LDDT<= Comparison In conductive status 6.400 12.800 5.500 9.700 of current...
Page 823 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When not executed 0.160 0.038 Comparison In conductive status 7.400 14.400 6.700 10.800 of specified In non-conductive status 7.400 14.400 6.700 10.800 ORDT>= date Comparison In conductive status 6.000 12.800...
Page 824 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. When not executed 0.160 0.038 Comparison In conductive status 7.200 13.900 6.300 10.800 of specified In non-conductive status 7.200 13.900 6.300 10.800 ANDTM> clock Comparison In conductive status 5.900 12.500...
Page 825 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. In conductive status Comparison 7.600 14.000 6.700 10.800 of specified In non-conductive 7.600 14.000 6.700 10.800 clock status LDTM>= Comparison In conductive status 6.200 12.700 5.400 9.500 of current...
Page 826 Processing Time (µs) Category Instruction Condition (Device) L02CPU, L02CPU-P L26CPU-BT, L26CPU-PBT Min. Max. Min. Max. RSET Standard RAM 3.500 11.100 2.700 5.900 No digit increase 9.000 17.900 4.600 7.000 DATE - Digit increase 10.000 19.200 4.600 6.500 SECOND –– 4.600 9.800 2.200 3.400...
Page 827 (2) Table of the time to be added when file register, extended data register, extended link register, module access device, and link direct device are used (a) When using L02CPU, L26CPU-BT, L02CPU-P, L26CPU-PBT Processing Time (µs) Device Device name Data Specification L02CPU, L26CPU-BT,...
Page 828 Appendix 2 CPU PERFORMANCE COMPARISON Appendix 2.1 Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU Appendix 2.1.1 Usable devices Device name QCPU LCPU AnUCPU AnACPU AnNCPU Q02H Q06H Q12H Q25H Q02PH –– Q06PH A2U: Q12PH Q00J: Q00UJ: L02CPU, –– A1N: 256 points 512 points Q25PH...
Page 829 Device name QCPU LCPU AnUCPU AnACPU AnNCPU Other than Universal model QCPU: 10 points 16 points (Z0 to Z15) 20 points 7 points (Z, Z1 to Z6) 1 point (Z) Index (Z0 to Z9) Universal model QCPU: 20 points (Z0 to Z19) register (Z0 to Z19) ––...
Page 830 Appendix 2.1.3 Data that can be used by instructions Setting Data QCPU LCPU AnUCPU AnACPU AnNCPU Bit device Bit data Word device –– –– –– (Bit specification (Bit specification required) required) Bit device (Digit specification (Digit specification (Digit specification (Digit specification (Digit specification Word data required)
Page 831 Appendix 2.1.4 Timer comparison Function QCPU/LCPU AnUCPU AnACPU AnNCPU 100ms (default value) Measurement Change of measurement unit at the parameter is Fixed at 100ms unit enabled. Low speed timer QCPU/LCPU: 1 to 1000ms (1ms unit) Designation K100 K100 method 10ms (default value) Change of measurement unit at the parameter is Measurement enabled.
Page 832 Example • For timers T0 to T2, the program is created in the order the timer operates later. T2 timer starts measurement from the next scan after turning the contact of T1 ON. T1 timer starts measurement from the next scan after turning the contact of T0 ON. T0 timer starts measurement when X0 is turned ON.
Page 833 Appendix 2.1.7 Instructions whose designation format has been changed (Except dedicated instructions for AnACPU and AnUCPU) Because the QCPU, LCPU does not have accumulators (A0, A1), the format of AnUCPU, AnACPU and AnNCPU instructions that used accumulators has been changed. QCPU/LCPU AnUCPU/AnACPU/AnNCPU Function...
Page 834 Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions (1) Method of expression of dedicated instructions Dedicated instructions based on the LEDA, LEDB, LEDC, SUB, and LEDR instructions, that are used with the AnACPU or AnUCPU have been changed for the same format as the basic instructions and the application instructions for the QCPU, LCPU.
Page 835 Appendix 3 APPLICATION PROGRAM EXAMPLES Appendix 3.1 Concept of Programs which Perform Operations of a nth power of X, a nth root X (1) Concept of programs which perform operations of X (nlogeX) can be operated using e (1.2 loge10) For example, the operation of 10 is e , which is represented in the form of a sequence program as shown...
Page 836 INDEX 0 to 9 BCD 8-digit multiplication and division operations . . 206 BCD 8-digit square roots ..... 540 16-bit BIN data decrement ....228 BCD type arc cosine operation .
Page 837 Complement of 2 of BIN 16-bit data Conversion from floating-point data to (sign inversion) ......246 BIN 16-bit data (Double precision) .
Page 838 Insertion of data in data tables ....423 Instructions whose designation format has been Encoding from 256 to 8 bits ....359 changed .
Page 839 Loading and unloading ..... . 656 Print ASCII code ......432 Loading program from memory card .
Page 840 Reading oldest data from tables ....419 Time data conversion (from Hour/Minute/Second to Reading routing information ....669 Second) .
Page 841 INSTRUCTION INDEX ......251 Symbols BKBIN(P) ......182 BKCMP .
Page 842 ......555 ......318 DBAND(P) DXOR(P) .
Page 843 ....... . . 132 ....... . . 132 .
Page 844 ....... 285 ....... . . 585 RFS(P) TM>...
Page 845 6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from Mitsubishi. 7. Any other failure found not to be the responsibility of Mitsubishi or that admitted not to be so by the user. 2. Onerous repair term after discontinuation of production (1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is discontinued.
Page 846 Microsoft, Windows, Windows NT are registered trademarks of Microsoft Corporation in the United States and other countries. Pentium and Celeron are trademarks of Intel Corporation in the United States and other countries. Ethernet is a trademark of Xerox Co., Ltd. in the United States. CompactFlash is a trademark of SanDisk Corporation.
Page 850 Phone: +380 (0)44 / 490 92 29 Fax: +380 (0)44 / 248 88 68 Mitsubishi Electric Europe B.V. /// FA - European Business Group /// Gothaer Straße 8 /// D-40880 Ratingen /// Germany Tel.: +49(0)2102-4860 /// Fax: +49(0)2102-4861120 /// info@mitsubishi-automation.com /// www.mitsubishi-automation.com...

Mitsubishi MELSEC-Q/L Programming Manual

Chapter 1 General Description

Chapter 2 Instruction Tables

Chapter 3 Configuration of Instructions

Chapter 4 How to Read Instructions

Chapter 5 Sequence Instructions

Chapter 6 Basic Instructions

Chapter 7 Application Instructions

Quick Links

Related Manuals for Mitsubishi MELSEC-Q/L

Summary of Contents for Mitsubishi MELSEC-Q/L