Fujitsu D3320 PRIMERGY BX2560 M2 Reference Manual page 20

Advanced menu
Disabled
Only memory resources below the 4 GB address boundary will be
assigned to the PCI devices. This selection is mandatory when
using a 32-bit operating system, but is also supported on 64-bit
operating systems.
Enabled
Memory resources above the 4 GB address boundary may be
assigned to PCI devices, which are capable of 64-bit address
decoding. This selection is supported only on 64-bit operating
systems. It may be required if the populated PCI Express devices
(e.g. coprocessors adapter cards) are claiming a huge amount of
memory resources, which no longer fits into the address space
below 4 GB.
I
The PCI address decoding of 32-bit operating systems is limited
by the 4 GB address boundary, even if the available PCI devices
would also support 64-bit address decoding.
DMI Control
Selects the speed of the bus connection between CPU and chipset.
Lower speed means less power consumption but also lower system
performance.
GEN1
The bus connection between CPU and chipset is configured to run
at 2.5GT/s.
GEN2
The bus connection between CPU and chipset is configured to run
at 5.0GT/s.
Memory Hole Size
Selects the memory hole size below the 4 GB address boundary. This
memory hole also includes allocated memory resources, requested by
PCI devices. The DRAM address space that was replaced by the
memory hole is remapped to above the 4 GB address boundary and still
useable.
2GB
The memory hole has a size of 2 GB. The remaining 2 GB address
space below the 4G address boundary is available for DRAM.
20 D3320 - BIOS Setup Utility
BX2560 M2