JVC RX-7030VBK Service Manual page 16

4.4 AK4112BVF-X (IC551) : Digital audio receiver
• Pin layout
DVDD 1
DVSS 2
3
TVDD
V/TX 4
XTI 5
XTO 6
PDN 7
R 8
AVDD 9
AVSS 10
RX1 11
RX2/DIF0 12
RX3/DIF1 13
14
RX4/DIF2
• Pin function
Pin No. Symbol I/O
1 DVDD - Digital Power Supply Pin 3.3V
2 DVSS - Digital Ground Pin
3 TVDD - Input Buffer Power Supply Pin 3.3V or
5V
4 V O Validity Flag Output Pin in Parallel
Mode
TX O Transmit channel (through data) Out-
put Pin in Serial Mode
5 XTI I X'tal Input Pin
6 XTO O X'tal Output Pin
7 PDN I Power-Down Mode Pin
When "L" the AK4112B is powered-
down and reset
8 R - External Resistor Pin
18kΩ +/-1% resistor to AVSS exter-
nally.
9 AVDD - Analog Power Supply Pin
10 AVSS - Analog Ground Pin
11 RX1 I Receiver Channel 1
This channel is selected in Parallel
Mode or default of Serial Mode.
12 RX2 I Receiver Channel 2 in Serial Mode
12 DIF0 I Audio Data Interface Format 0 Pin in
Parallel Mode
13 RX3 I Receiver Channel 3 in Serial Mode
13 DIF1 I Audio Data Interface Format 1 Pin in
Parallel Mode
14 RX4 I Receiver Channel 4 in Serial Mode
14 DIF2 I Audio Data Interface Format 2 Pin in
Parallel Mode
15 AUTO O Non-PCM Detect Pin
"L": No detect "H": Detect
16 P/S I Parallel/Serial Select Pin
"L": Serial Mode "H": Parallel Mode
1-16 (No.22058)
28 CM0/CDTO
27 CM1/CDT1
26
OCKS1/CCLK
25 OCKS0/CSN
24 MCKO1
23
MCKO2
22 DAUX
21 BICK
20
SDTO
19 LRCK
18 ERF
17 FS96
16 P/SN
15 AUTO
Function
Pin No. Symbol I/O
17 FS96 O 96kHz Sampling Detect Pin
(RX Mode)
"H": fs=88.2kHz or more
"L": fs=54kHz or less.
(X'tal Mode) "H": XFS96=1
"L": XFS96=0.
18 ERF O Unlock & Parity Error Output Pin
"L": No Error "H": Error
19 LRCK I/O Output Channel Clock Pin
20 SDTO O Audio Serial Data Output Pin
21 BICK I/O Audio Serial Data Clock Pin
22 DAUX I Auxiliary Audio Data Input Pin
23 MCK02 O Master Clock #2 Output Pin
24 MCK01 O Master Clock #1 Output Pin
25 OCKS I Output Clock Select 0 Pin in Parallel
0 Mode
CSN I Chip Select Pin in Serial Mode
26 OCKS I Output Clock Select 1 Pin in Parallel
1 Mode
CCLK I Control Data Clock Pin in Serial Mode
27 CM1 I Master Clock Operation Mode Pin0 in
Parallel Mode
CDTI I Control Data Input Pin in Serial Mode
28 CM0 I Master Clock Operation Mode Pin1 in
Parallel Mode
CDTO O Control Data Output Pin in Serial
Mode
NOTE:
All input pins except internal pull-down pins should not be
left floating.
Function