Denon ADV-700 Service Manual page 28
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Also See for ADV-700:
- Operating instructions manual (318 pages) ,
- Service manual (128 pages) ,
- Brochure & specs (6 pages)
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Pin No.
Pin Name
I/O
µcom address input
95
MA4
I
µcom address input
96
MA5
I
µcom address input
97
MA6
I
98
/MCE
I
Chip enable signal input
µcom chip read signal input
99
/MRD
100
V
GND pin
SS
µcom write signal input
101
/MWR
I
µcom interrupt signal output, open drain, pull-up R built-in
102
/MINT
O
103
TESTOUT
O
Output for test, leave it open
104
/RST
I
Hardware reset input (CMOS level), pull-up R built-in
105
V
Power pin
DD
106
V
GND pin
SS
107
V
GND pin
SS
108
NC
109
V
Power pin
DD
110
HD7
I/O
111
HD8
I/O
112
HD6
I/O
Host data in/output (HD [0:15] : IDE sig. DD [0:15]), TTL level, tri-statte out, pull-up R built-in
113
HD9
I/O
114
HD5
I/O
115
HD10
I/O
116
V
GND pin
SS
117
HD4
I/O
118
HD11
I/O
119
HD3
I/O
120
HD12
I/O
121
HD2
I/O
Host data in/output (HD [0:15] : IDE sig. DD [0:15]), TTL level, tri-statte out, pull-up R built-in
122
HD13
I/O
123
HD1
I/O
124
HD14
I/O
125
HD0
I/O
126
V
Power pin
DD
127
V
GND pin
SS
128
HD15
I/O
Host data in/output (HD [0:15] : IDE sig. DD [0:15])
129
HDRQ
O
Data request output: IDE sig. DMARQ, tri-state out, drive-ability 12mA
130
/HWR
I
Host write signal input: IDE sig. /DIOW, TTL level, pull-up R built-in
131
V
hr
GND pin (for /HR)
SS
132
/HRD
I
Host read signal input: IDE sig. /DIOR, TTL level, pull-up R built-in
133
V
24
GND pin (for IORDY)
SS
134
IORDY
O
IO transfer ready output: IDE sig. IORDY, tri-state out, drive-ability 24mA
135
V
Power pin (for IORDY)
DD24
136
V
GND pin
SS
137
/HDAK
I
Data acknowledge input: IDE sig. /DMACK, TTL level, pull-up R built-in
138
INTRQ
O
Interrupt signal output: IDE sig. INTRQ, tri-state out, drive-ability 12mA
139
/IOCS16
O
Data bit wide select output: IDE sig. /IOCS16, open drain, pull-up R built-in
140
HA1
I
Host address 1 input: IDE sig. DA1, TTL level, pull-up R built-in
141
/PDIAG
I/O
Post diagnostic in/output: IDE sig. /PDIAG, TTL level, tri-state out, pull-up R built-in
142
HA0
I
Host address 0 input: IDE sig. DA0, TTL level, pull-up R built-in
143
VDD
Power pin
144
NC
* Pin names begin with
PSYNCN, and PDRQN are active L terminals.
Function
ADV-700
28
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