Denon ADV-700 Service Manual page 21

Pin No. Pin Name I/O
56 DMA 3 O DRAM address bus
57 DMA 4 O DRAM address bus
58 DMA 5 O DRAM address bus
59 Vcc I 3.6V power supply
60 Vss I GND
61 DMA 6 O DRAM address bus
62 DMA 7 O DRAM address bus
63 DMA 8 O DRAM address bus
64 DMA 9 O DRAM address bus
65 DMA 10 O DRAM address bus
66 DMA 11 O DRAM address bus
67 Vss I GND
68 Vcc I 3.6V power supply
69 DCAS# O Column address strobe, active low
DOE# O Output enable, active low
70
DSCK_EN I Clock enable, active low
71 DWE# O DRAM write enable, active low
72 DRAS 0# O Row address strobe, active low
73 DRAS 1# O Row address strobe, active low
74 DRAS 2# O Row address strobe, active low
75 Vcc I 3.6V power supply
76 Vss I GND
77 DB 0 I/O DRAM data bus
78 DB 1 I/O DRAM data bus
79 DB 2 I/O DRAM data bus
80 DB 3 I/O DRAM data bus
81 DB 4 I/O DRAM data bus
82 DB 5 I/O DRAM data bus
83 Vcc I 3.6V power supply
84 Vss I GND
85 DB 6 I/O DRAM data bus
86 DB 7 I/O DRAM data bus
87 DB 8 I/O DRAM data bus
88 DB 9 I/O DRAM data bus
89 DB 10 I/O DRAM data bus
90 DB 11 I/O DRAM data bus
91 Vss I GND
92 Vcc I 3.6V power supply
93 DB 12 I/O DRAM data bus
94 DB 13 I/O DRAM data bus
95 DB 14 I/O DRAM data bus
96 DB 15 I/O DRAM data bus
97 DCS 1# O SDRAM chip select [1], active low
98 Vss I GND
99 Vcc I 3.6V power supply
100 DCS 0# O SDRAM chip select [0], active low
101 DQM O Data input/output mask
102 DSCK O Clock to SDRAM
103 Vss I GND
104 Vcc I 3.6V power supply
105 DCLK I Clock input (27MHz)
106 YUV 0 O 8-bit YUV output
107 YUV 1 O 8-bit YUV output
Function Pin No.
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
Pin Name I/O
YUV 2 O 8-bit YUV output
YUV 3 O 8-bit YUV output
YUV 4 O 8-bit YUV output
Vcc I 3.6V power supply
Vss I GND
YUV 5 O 8-bit YUV output
YUV 6 O 8-bit YUV output
YUV 7 O 8-bit YUV output
PCLK2XSCN I/O 2X pixel clock
PCLKQSCN I/O Pixel clock
Vertical sync for screen video interface,
VSYNCH# I/O programmable for rising or falling edge,
active low
Horizontal sync for screen video
HSYNCH# I/O interface, programmable for rising or
falling edge, active low
Vss I GND
Vcc I 3.6V power supply
HD 0 I/O Host data bus
HD 1 I/O Host data bus
HD 2 I/O Host data bus
HD 3 I/O Host data bus
HD 4 I/O Host data bus
HD 5 I/O Host data bus
HD 6 I/O Host data bus
Vss I GND
Vcc I 3.6V power supply
HD 7 I/O Host data bus
HD 8 I/O Host data bus
HD 9 I/O Host data bus
HD 10 I/O Host data bus
HD 11 I/O Host data bus
HD 12 I/O Host data bus
HD 13 I/O Host data bus
Vss I GND
Vcc I 3.6V power supply
HD 14 I/O Host data bus
HD 15 I/O Host data bus
HWRQ# O Host write request
HRDQ# O Host read request
HIRQ I/O Host interrupt
HRST# O Host reset
HIORDY I Host I/O ready
Vss I GND
Vcc I 3.6V power supply
HWR# O Host write request
Host write / DCI interface acknowledge
HWR#/DCI_ACK# I, I
signal, active low
HRD#/DCI_CLK I, I Host read / DCI interface clock
HIOCS16# I Device 16-bit data transfer
HCS1FX# O Host select 1
HCS3FX# O Host select 3
HA 0 I/O Host address bus
HA 1 I/O Host address bus
ADV-700
Function
21