Pll Circuits; Other Circuits - Icom IC-U82 Service Manual

4-3 PLL CIRCUITS

4-3-1 GENERAL
PLL circuits control the VCO circuit. IC19 is a PLL IC and
contains prescaler, programmable counter, programmable
divider, phase detector, charge pump in its package.
The VCO (Q76, D59, D60) directly generates both of the
transmit frequency and the 1st LO frequency.
The PLL sets the divided ratio based on the N-data from the
CPU (IC8), and compares the phase of the VCO output with
the reference frequency (15.3 MHz) generated by X4.
If the oscillated signal drifts, the phase of its frequency
changes from the phase of the reference frequency, causing a
lock voltage change to compensate for the drift in the oscil-
lated frequency.
4-3-2 TRANSMIT LOOP
A portion of the generated signal at the VCO (Q76, D59, D60)
is applied to the PLL IC (IC19, pin 8) via buffer-amplifiers
(Q5, Q75). The applied signal is divided at the prescaler sec-
tion and programmable divider section, then applied to the
phase detector section.
The phase detector compares the input signal with the
reference frequency, and then outputs the control signal
(pulse-type) from pin 5 via the charge pump section. The
pulse-type signal is converted into DC voltage at the loop fil-
ter (R445–R448, C472–C474), and then applied to the VCO
(Q76, D59, D60) as the lock voltage.
4-3-3 RECEIVE LOOP
The generated 1st LO signal is applied to the PLL IC (IC19,
pin 8) via the buffer-amplifiers (Q5, Q75) and is divided at
the prescaler section and the programmable divider section,
then applied to the phase detector section.
• PLL CIRCUITS
Buffer
Q34
"LOINV" signal
to the CPU (IC661, pin 34)
45.9 MHz 2nd LO
signal to the FM IF IC
(IC2, pin 2)
Q81
VCO
Q76, D59, D60
Loop
filter
Programmable
5 Charge
pump
Phase
detector
2
×3
The phase detector compares the input signal with the
reference frequency, and then outputs the control signal
(pulse-type) from pin 5 via the charge pump section. The
pulse-type signal is converted into DC voltage at the loop fil-
ter (R445–R448, C472–C474), and then applied to the VCO
(Q76, D59, D60) as the lock voltage.

4-4 OTHER CIRCUITS

4-4-1 CTCSS/DTCS CIRCUIT (DECODING)
The CTCSS/DTCS signal from FM IF IC (IC2, pin 9) is fil-
tered at the LPF (Q53). The filtered signal is then applied to
the CPU (IC8, pin 5) to control the AF amplifier according to
the received CTCSS/DTCS signal.
4-4-2 CTCSS/DTCS CIRCUIT (ENCODING)
• CTCSS
The CTCSS signal is generated by the CPU (IC8) and output
from pin 139 and passed through the LPF (R224, C126, C129)
and CTCSS switch (Q38). The CTCSS signal is then applied
to the splatter filter (IC3, pin 13) to be mixed with the micro-
phone audio signals. The filtered CTCSS signal is then
output from pin 14 and applied to the digital/analog switch
(IC15, pins 8, 9 and pins 3, 4) via the analog switch (IC4;
pins 8, 9).
The CTCSS signal from the digital/analog switch (IC15, pin 3)
is applied to the D/A converter (IC10, pin 21) to adjust its
level. The level adjusted CTCSS signal is then applied to the
modulator circuit (D61).
• DTCS
The DTCS signal is also generated by the CPU (IC8) and
output from pin 139. The DTCS signal is applied to the
DTCS amplifier (IC23, pin 3) via DTCS switch (IC16, pins 1,
7). The amplified DTCS signal is applied to the D/A convert-
er (IC10, pin 13) to adjust its level. The level adjusted DTCS
signal is then applied to both of the modulator circuit (D61)
and the reference frequency oscillator (X4).
Buffer
Q75
IC19 MB15E03SL
8
Prescaler
divider
9
10
Shift register
11
1
4 - 3
D4
Buffer
to 1st mixer circuit
Q74
D3
to transmitter circuit
Buffer
Q5
LPF
PLLCK
PLL control signals
PLLDATA
from the CPU (IC8, pins 68–70)
PLLSTB
15.3 MHz reference signal
from reference frequency osciilator (X4)