Advertisement
Block Diagram
6-2 DLP-Builtin Module
PCMCIA
Cable Card
POD Channel
nnel
(NT & AT SC& QAM )
Scramle TS
T UNE
UNER
#2
TS_1_DATA [ 7: 0]
M
CImax
U
(N T )
CLK ,V LD,SYNC
X
Card I/ F
TUNER SIGNAL
M_CVBS
M
S_CVBS
U
M_SIF
X
S_SIF
TS_2_DATA [7:0]
VIDEO-1
CLK ,V L D,SYNC
3D-Y
3D-C
VIDEO-2
SUB-V/ Y
3D- Y/ C
SUB-C
SUB - Y/ C
S_CV BS
Componet-1
COMP1_Y
COMP1 Y,Pb,Pr
COMP1_Pb
COMP2 Y,Pb,Pr
COMP1_Pr
Componet-2
BA7657
COMP1 Y,Pb,Pr
COMP2_Y
COMP2 Y,Pb,Pr
CO M P
COMP2_Pb
COMP2_Pr
S/ W
HDM I R x
TMD S
M
U
X
HDMI
Sii9993
RS-232
M
TMDS
HD MI Rx
U
MIC OM_ R x
X
MIC OM_ T x
RS-232(Debug)
Rx
Tx
6-2
UN Scramle TS
M
TS_A_DATA [ 7: 0]
U
X
CL K ,V L D,SYNC
M
TS_B_DATA [ 7: 0]
U
X
CL K ,V L D,SYNC
ADV7400
400
#2
(NT & ADC)
76 57
Y,Pb,Pr
3D- Y/ C
SUB - Y/ C
ADV7400
400
S_CV BS
#1
7657 Y,Pb,Pr
(NT & ADC)
PC R,G,B ,
HSYNC,V SYNC
I2C_M
I2C
SDA _M5
SDA _PANNEL
SCL _M5
SCL _PANNEL
FL
FL A SH
RA
RAM
(128
128 M B )
(16 M B )
28 F 128
K4D 551638D x2
TS # A
TS # B
&
Ext
Di git al
VI DEO
X226 B
X226
OUT
IN # A
(
CP
CPU
MU X
&
MPEG.
MP
G. de c ode r
&
AU DIO
Vide o Sc aler
65 6[7 :0 ] ,CL K
OUT
&
OSD
)
AC 3 /PCM
OU T
Ext
65 6[7 :0 ] ,CL K
VI DEO
or
24 bit [ 7: 0],CL K ,
IN #B
HSync,V sync
DE
Ext
AUDIO
RS- 232 A
IN
RS- 232 B
HDMI_I2S_CLK ,
MI COM_Rx, T x
DAT A ,L RCLK
MUX
NT _I2S_CL K ,
DATA ,L RCLK
AUDIO
I2S_CLK,DATA,LRCLK
NT_I2S_CLK,
DATA,LRCLK
MEMO
MEMORY
(1 (16MB) B)
K4S643232 x 2
1 2bi t[ 24: 12 ]
H,V SYNC, CL K 1
24 bi t
DN Ie Pro
DN
[ 23: 0]
12 bi t
D-Flip
Image
H,VSYN C,
[11 :0 ]
-Fl o p
Enhancer
12 bi t
CLK
CLK 0
[11 :0 ]
I2S_CL K ,DATA
LR C L K
OPT ICA L
AC 3 /PCM
/RC A
OU T
LVDS &
LVD
MD_
MD_Contr
ntrol
TX[3:0 ]+-
DLP _SYNCVAL
MD_nRESET
DDP _ READY
PWRGOOD
LVDS_EN
LAM P+Txn,Rx
SDA,SCL PANNEL
Rx,Tx
AUDIO
AUD
SPDIF
CONTROL
I2C_5V
CPU_RESET
SDA_M5
SCL _M5
Samsung Electronics
TH C6 3LVDH6 3
LVDS Tx
Hide quick links:
Advertisement
