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A machine-check exception may or may not be taken for each assertion of BINIT# as configured
in software.
The BERR# pin is used to signal any error condition caused by a bus transaction that will not
impact the reliable operation of the bus protocol (for example, memory data error, non-modified
snoop error). A bus error that causes the assertion of BERR# can be detected by the processor,
or by another bus agent. The BERR# driver can be enabled or disabled at power-on reset. If the
BERR# driver is disabled, BERR# is never asserted. If the BERR# driver is enabled, the Pen-
tium Pro processor may assert BERR#.
A machine check exception may or may not be taken for each assertion of BERR# as configured
at power on. The Pentium Pro processor will always disable the machine check exception by
default.
If a Pentium Pro processor detects an internal error unrelated to bus operation, it asserts IERR#.
For example, a parity error in an L1 or L2 cache causes a Pentium Pro processor to assert IERR#.
A machine check exception may or may not be taken for each assertion of IERR# as configured
with software.
Two Pentium Pro processors may be configured as an FRC (functional redundancy checking)
pair. In this configuration, one processor acts as the master and the other acts as a checker, and
the pair operates as a single, logical Pentium Pro processor. If the checker Pentium Pro processor
detects a mismatch between its internally sampled outputs and the master Pentium Pro proces-
sor's outputs, the checker asserts FRCERR. FRCERR observation can be enabled at the master
processor with software. The master enters machine check on an FRCERR provided that Ma-
chine Check Execution is enabled.
The FRCERR signal is also toggled during the Pentium Pro processor's reset action. A Pentium
Pro processor asserts FRCERR one clock after RESET# transitions from its active to inactive
state. If the Pentium Pro processor executes its built-in self test (BIST), then FRCERR is assert-
ed throughout that test. When BIST completes, the Pentium Pro processor desserts FRCERR if
BIST succeeds and continues to assert FRCERR if BIST fails. If the Pentium Pro processor does
not execute the BIST action, then it keeps FRCERR asserted for less than 20 clocks and then
deasserts it.
3.4.9.
Compatibility Signals
The compatibility signals group (see Table 3-18) contains signals defined for compatibility with-
in the Intel architecture processor family.
Type
Floating-Point Error
Ignore Numeric Error
Address 20 Mask
System Management Interrupt
Table 3-18. PC Compatibility Signals
BUS OVERVIEW
Signal Names
FERR#
IGNNE#
A20M#
SMI#
Number
1
1
1
1
3-23
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