Front Panel Interface; Bias Supply And Start Up - Agilent Technologies 6622A Service Manual

appears on data bus lines D0-D3, respectively, and
EEPROM serial output data appears on data bus line D7.
Logic 0's will always appear on data bus lines D4-D6 when
____
CS3 is decoded because these buffer inputs are connected to
COMMON. All buffer outputs are held in the high
____
impedance state when CS3 is not decoded.
2-18 Data Latches. These stages (U213) are edge-triggered
D-type flip-flops. On the rising edge of the CS2 chip select,
the output of each stage will be set to the logic state that is
present on the associated data bus line. Data bus lines D0-
D3 are the serial data input lines for output boards 1-4,
respectively. Data bus line D4 controls the TIMER ENABLE
signal line to the real time clock circuit; D5 is the chip select
line for the EEPROM; D6 is the clock signal for the
EEPROM; and D7 is the data input line for the EEPROM.
The data that is transferred between the GPIB board and
the output boards (up to 4) passes through optical isolators
located on each output board.
2-19 EEPROM. This 1 K bit serial EEPROM (electrically
erasable programmable memory) stores the power supply's
GPIB address and model number as well as the constants
used in calibrating the supply. The EEPROM (U221) is non-
volatile allowing it to retain the stored information after
power is cycled off and on.
Because the RAM operates faster than the EEPROM, at
power on, the stored serial data is read into RAM in the
system microcomputer via data bus line D7, the associated
buffer state, and the data output pin of the EEPROM.
The EEPROM's 1024 bits of read/write memory are divided
into 64 registers of 16 bits each. Each register can be serially
read from or written to using data bus line D7. Input data is
received via a data latch and output data is sent via a data
buffer.
Data written to the EEPROM is stored in a location until it is
updated by an erase and write cycle. The CHIP SELECT and
CLOCK signals are used by the microprocessor to control
the EEPROM's programming modes. At power on, the
EEPON signal holds the EEPROM's CLOCK signal off to
protect against accidental data writes when power is
initially applied.
2-20

Front Panel Interface

These circuits provide the interface between the supply's
system microcomputer and the front panel (keyboard and
LCD display). The microprocessor uses the data latches
(U210) and data buffers (U214) to transfer data between the
supply's system microcomputer and the front panel.
2-21 Data Latches. On the rising edge of the CS5 chip select
these D-type flip-flops will be set to the logic states that are
present on the data bus lines.
Data bus lines D2-D7 are fed directly to the front panel
display to indicate power supply conditions. The LCD
display may indicate the output voltage and current for a
selected
programmed, a programmed message, or an error message.
The annunciators provide operating and status information.
The microprocessor uses the real time clock to determine
when to update/refresh the display.
Data bus lines D0-D2 are fed to the 3 to 8 line keyboard
decoder (U211). The microprocessor successively drives
____
each of the eight open collector outputs of the decoder and
monitors the four readback lines from the keyboard to
determine which key was pressed. The readback lines are
held high until a depressed key pulls the line low.
______________
2-22 Data Buffers. These 3-state buffers place the keyboard
readback data on data bus lines D4-D7 when chip select CS4
is decoded. As stated above, the microprocessor will use this
information to determine which key was pressed. In
addition to the keyboard readback data on D4-D7, the front
panel data buffers provide the following data on bus lines
D0-D3 when CS4 is decoded:
All buffer outputs are held in the high impedance state
disconnecting it from the data bus when CS4 is not decoded.
2-23 Bias Supply and Start-Up Circuit
The bias supply (U218) provides + 5 V bias power to operate
the circuits on the GPIB board. The start-up circuit
(U220,U222) generates the OPTO PON signal (delayed + 5
V) which is used to power the optical-isolators on the
output boards. The OPTO PON signal is initially held low
for approximately 100 ms to prevent the erroneous transfer
of data at power on. The start-up circuit also generates
______
PCLR (power clear) and EEPON (EEPROM power on)
signals when power is turned on. The PCLR signal is held
low at power on to initialize the talker/listener and
microprocessor chips. The EEPON signal is held low at
____
power on to disable the EEPROM clock. Thus, the start up
circuit
optoisolators until the bias voltages have stabilized. If the
line voltage drops after the unit has been turned on, the
start-up circuit will again generate the low level signals to
disable the interface and remove power from the supply's
outputs.
2-5
output board, the
____
D0 - A logic 1 (Jumper W201 is not installed in the
Skip Self Test position)--tells the microprocessor
to perform the self test at power on;
or
a logic 0 (Jumper W201 is installed in the Skip
Self Test position) - tells the microprocessor not
to perform self test at power on.
D1 - A logic 1 (jumper W201 is not installed in the Cal
Lockout position) - tells the microprocessor to
respond to calibration commands;
or
a logic 0 (Jumper W201 is installed in the Cal
Lockout position) - tells the microprocessor to
ignore calibration commands. This jumper
provides security
calibration.
D2 - A logic 1 (this buffer input is hardwired).
D3 - A logic 0 (this buffer input is hardwired).
delays turning on
present function being
____
against unauthorized
____
the microprocessor and