System Clocks - Philips DVDR985 Technical Training Manual

Figure 34 - Power Clock and Reset of the Digital Signal Processor

System Clocks

The System Clocks (27MHz) of the VSM,
EMPRESS, and Progressive Scan circuits are
generated by an oscillator, 7906. Refer to Figure
35. The clock signal is buffered and inverted by
7904, a quad inverter. These signals go to their
respective circuits as SYSCLK_XXXX. During
record mode, the audio clock, ACC_ACLK_OSC
is generated by IC7102. The audio clock must
be synchronized with the incoming Video Field
Identifier, VIP_FID. During playback mode, the
audio clock, ACC_ACLK_PLL, is generated by
the clock synthesizer, IC7900. Both,
ACC_ACLK_OSC (also goes to the EMPRESS
as ACLK_EMP) and ACC_ACLK_PLL are fed to
the VSM. The VSM selects the appropriate
clock. The EMPRESS IC derives from the incom-
ing ACLK_EMP clock the I 2 S audio encoder Bit
clock and Word clock, AE_BCLK and AE_WCLK.
They are sent to the VSM.
On/Off
The signal IOn, coming from the Analog Board's
microcomputer, enables the switched power sup-
plies. IOn goes Low to turn power On. The
switched supplies are: the 5Vdc and 12Vdc on
this module.
Reset
Control signal IRESET_DIG, controlled by the
microcomputer on the Analog Board is sent to
the Reset Logic circuit. The IRESET_DIG transi-
tions to High when the whole system is reset. A
Low is output on Pin 1 of 7902. This signal is
labeled RESETn. The n on the end of many of
the names of the signal lines means enable.
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