Philips DVDR985 Technical Training Manual page 101

Digital Video Input Board
The DVIO Module is a decoder for DV streams.
DV from a camcorder, IEEE1394, input stream
is converted to CCIR656 Video and Analog
Audio (L+R). A serial control interface is present.
Block Diagram
The DVIO module consists of the following
blocks, Refer to Figure 55. An Independent tun-
able audio and video clock is used for FIFO and
PLL. A Microcomputer using an 8051 CPU with
64 kilobyte of flash memory controls the whole
operation. It also has 1 kilobyte of internal data
memory. There is a Watchdog timer and PCA
outputs. The System Clock runs at 11.0592MHz.
On board In Circuit Programming, ISP, can be
used to update the EEPROM, Downloading.
Clock Circuit
There are two clocks to consider in the system,
the video clock and the audio clock. These two
clocks are independent and will be discussed
separately. The video clock is approximately 27
MHz. When data is flowing from an external
source, it does not have exactly the same fre-
quency and phase. This could cause buffers to
under-run or over-run. Since the clock cannot be
modified in the source the clock is adjusted to
the required frequency and phase to process at
the rate of the incoming data. The same require-
ments apply to the audio clock. The audio clock
operates at three frequencies. The source can
have a frequency of 8.192 MHz, 11.2896 MHz,
or 12.228 MHz. This depends on the sample-rate
frequency 32kHz, 44.1kHz, or 48kHz, of the
Audio signal.
FIFO and Control
In decode mode, an asynchronous AV-stream is
flowing through the IEEE1394 Interface into the
FPGA. The FPGA stores the data in a First In
First Out buffer. Each buffer holds one whole
frame each.
DV Decoder
The AV data goes from the FIFO to the NW700.
It decodes the stream into video data in 656 for-
mat. The Microcomputer has the ability to read
the status registers of the NW700 through the
FPGA. By reading these registers extra data
from the DV stream, that is not decoded into
audio or video, can be sent to the Digital Board,
using TXD of the serial interface. This includes
Time Stamp and other simular data.
Audio and Video Output
The Audio I 2 S data is sent to an Audio DAC,
UDA1334. Analog audio Left and Right signals
are sent to the Analog Board. The Tri-State
Buffer enables the Digital Video stream to go to
the Video Input Processor on the Digital Board
when the DV source is selected. The clock
delay synchronizes the AV clock with the AV data
at the output.
92