LG -T510 Service Manual page 42

[ DDR SDRAM ]
• Double Data Rate architecture
- two data transfer per clock cycle
• x16 bus width
• Supply Voltage
- VDD / VDDQ = 1.7 - 1.95 V
• Memory Cell Array
- 16Mb x 4Bank x 16 I/O
• Bidirectional data strobe (DQS)
• Input data mask signal (DQM)
• Input Clock
- Differential Clock Inputs (CK, /CK)
• MRS, EMRS
- JEDEC Standard guaranteed
• CAS Latency
- Programmable CAS latency 2 or 3 supported
• Burst Length
- Programmable burst length 2 / 4 / 8 with both sequential and interleave mode
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