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MCP2-1_2G_1G DDRx16_hynix
VDD_IO_1V8
VDD_IO_1V8
VDD_IO_1V8
LGE Internal Use Only
U301
EAN61927501
H9DA2GH1GHMMMR-46M
A8
J4
TP301
VDD1
A0
NANDD_DDRA[00]
C1
K1
VDD2
A1
NANDD_DDRA[01]
G1
K2
VDD3
A2
C301
C302
C303
C304
NANDD_DDRA[02]
G10
K3
VDD5
A3
4.7u
0.1u
0.1u
0.1u
NANDD_DDRA[03]
L1
B2
VDD4
A4
NANDD_DDRA[04]
N8
C2
VDD6
A5
NANDD_DDRA[05]
D1
A6
NANDD_DDRA[06]
B9
C3
VDDQ1
A7
NANDD_DDRA[07]
C10
D2
VDDQ6
A8
NANDD_DDRA[08]
D9
C4
VDDQ5
A9
NANDD_DDRA[09]
C306
C307
C308
C309
E10
J3
VDDQ4
A10
NANDD_DDRA[10]
4.7u
0.1u
0.1u
0.1u
F9
E2
VDDQ10
A11
NANDD_DDRA[11]
H10
E1
VDDQ9
A12
NANDD_DDRA[12]
J9
H3
VDDQ2
BA0
NANDD_DDRA[14]
K9
J2
VDDQ8
BA1
NANDD_DDRA[15]
L10
VDDQ7
M9
K4
TP302
VDDQ3
DQ0
DDR_D[00]
K5
DQ1
DDR_D[01]
K6
DQ2
DDR_D[02]
A2
K7
NC27
DQ3
DDR_D[03]
D4
J8
NC20
DQ4
DDR_D[04]
D6
K8
NC21
DQ5
DDR_D[05]
E3
J7
NC9
DQ6
DDR_D[06]
E4
J5
NC19
DQ7
DDR_D[07]
E5
E6
NC8
DQ8
DDR_D[08]
E7
C5
NC11
DQ9
DDR_D[09]
E8
D8
NC12
DQ10
DDR_D[10]
F1
C6
NC17
DQ11
DDR_D[11]
F3
C8
NC18
DQ12
DDR_D[12]
F4
C7
NC7
DQ13
DDR_D[13]
F5
B8
NC16
DQ14
DDR_D[14]
F6
B7
NC25
DQ15
DDR_D[15]
F7
NC6
G3
G8
NC10
/CK
DDR_CLK_N
G4
F8
NC5
CK
DDR_CLK_P
G5
D3
TP305
NC13
CKE
DDR_CKE
G6
H2
TP306
NC14
/CS
DDR_CS_N
G7
F2
NC4
/RAS
DDR_RAS_N
H4
G2
NC2
/CAS
DDR_CAS_N
H5
J1
NC24
/WED
TP307
NAND_DDR_WE_N
H6
D7
NC22
UDQM
DDR_DQM[1]
J6
H8
NC23
LDQM
DDR_DQM[0]
L3
D5
NANDD_DDRA[13]
A13
UDQS
DDR_DQS[1]
L4
H7
NC3
LDQS
DDR_DQS[0]
A5
M1
TP308
VCC1
IO0
NANDD_DDRA[00]
M5
M2
VCC2
IO1
NANDD_DDRA[01]
M3
C311
C312
C313
IO2
NANDD_DDRA[02]
L5
0.1u
0.1u
0.1u
IO3
NANDD_DDRA[03]
N7
IO4
NANDD_DDRA[04]
L6
IO5
NANDD_DDRA[05]
VDD_IO_1V8
A9
M6
VSS1
IO6
NANDD_DDRA[06]
B1
L8
VSS4
IO7
NANDD_DDRA[07]
B5
N2
VSS8
IO8
NANDD_DDRA[08]
B10
N3
VSSQ5
IO9
NANDD_DDRA[09]
C9
M4
VSSQ4
IO10
NANDD_DDRA[10]
D10
N4
VSSQ9
IO11
NANDD_DDRA[11]
E9
N5
VSSQ8
IO12
NANDD_DDRA[12]
F10
M7
VSSQ3
IO13
NANDD_DDRA[13]
G9
L7
VSS2
IO14
NANDD_DDRA[14]
H1
M8
VSS3
IO15
NANDD_DDRA[15]
H9
VSSQ10
J10
A6
VSSQ1
/CE
NAND_CS_N
K10
A3
TP309
VSSQ2
/RE
NAND_RE_N
L2
A7
VSS5
/WE
TP310
NAND_DDR_WE_N
L9
A4
TP311
VSSQ6
CLE
NAND_CLE_N
M10
B4
TP312
VSSQ7
ALE
NAND_ALE_N
N6
B3
VSS6
/WP
NAND_WP_N
N9
B6
VSS7
R/B
NAND_BSY_N
8-3-1-2_Push_168T_Ver1.0
Micro_SD
VMMC_2V85
VMMC_2V85
R302
R303
R304
R305
R306
S301
56K
56K
56K
56K
56K
G7
G5 G3 G1
MSD_D[2]
1
MSD_D[3]
2
MSD_CMD
3
4
5
MSD_CLK
6
MSD_D[0]
7
MSD_D[1]
8
G6 G4 G2
C305
C320
C321
C322
C323
C324
1u
33p
33p
33p
33p
33p
SIM_CONNECTOR 1(Default)
2V85_VSIM
2V85_VSIM
R307
J301
4.7K
C5
C1
GND1
VCC
C6
C2
VPP
RST
C7
C3
SIM_DATA_1
IO
CLK
C12
C9
C314
GND5
GND2
C315
C11
C10
22p
GND4
GND3
0.1u
C316
DNI
ZD200ZD201 is DNI defaultly
These are added for CMCC ESD test
SIM_CONNECTOR 2
2V85_VSIM
2V85_VSIM
R314
J302
4.7K
C5
C1
GND1
VCC
C6
C2
VPP
RST
C7
C3
SIM_DATA_2
IO
CLK
C12
C9
C317
GND5
GND2
C318
C11
C10
22p
GND4
GND3
0.1u
C319
DNI
ZD200ZD201 is DNI defaultly
These are added for CMCC ESD test
- 142 -
VDD_IO_1V8
R301
100K
CD
MSD_DET_N
C1
15
C2
C3
C4
VA301
C5
C6
C7
C8
16
COM
ENSY0023601
2V85_VSIM
C310
1u
U302
SIM_RST_N
SIM_CLK
2B1
1B1
SIM_DATA_2
4
6
SIM_RST_2
2A
1A
SIM_DATA
3
7
C325
22p
SIM_RST_SEL
SIM_SEL
2S
1S
2
8
2B0
1B0
SIM_DATA_1
1
9
R309
R310
100K
100K
SIM_RST_2
SIM_CLK
Copyright © 2011 LG Electronics. Inc. All right reserved.
8. CIRCUIT DIAGRAM
Only for training and service purposes
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