External Memory Interface - LG GT540 Service Manual

3. TECHNICAL BRIEF

3.11 External memory interface

3.11.1. MSM7227
The MSM7227 device was designed to provide two distinct memory interfaces. EBI1 was targeted for supporting
DDR synchronous memory devices. EBI2 was targeted towards supporting slower asynchronous devices such as LCD,
NAND flash, SRAM, NOR flash etc. To support the high-bandwidth, high-density, and low-latency requirements of
the advanced on-chip applications, the MSM7227 IC has two high-speed, high-performance memory slave
interfaces: the external bus interface 1 (EBI1) and the stack memory interface (SMI). To achieve higher bandwidth
and better use of the memory device interface, the SMI accepts multiple commands for the external memory
device. The SMI interface acts as a slave device to all of the bus masters within the MSM device. The masters arbitrate
to gain access to the SMI, and upon obtaining the access, they issue commands to the SMI. The bus masters are
connected to the SMI through an advanced extensible interface (AXI) bus bridge (or global interconnect block) and
communicate over a 64-bit, non-blocking AXI bus protocol. The AXI bus bridge provides the arbitration logic for all
of the bus masters.
EBI1 Features
- Support for only low-power memories at 1.8-V I/O power supply voltage
- AXI bus frequencies up to 133 MHz
- A 16-bit/32-bit static and dynamic memory interface
DDR SDRAM interface features include:
- Supports both 32-bit DDR SDRAM devices, up to 133-MHz bus speed
- Supports auto precharge and manual precharge
- Supports partial refresh
- Separate CKE pin per chip-select to support partial operation mode
- Idle power down to save idling power consumption
EBI2 Features
- Support for asynchronous FLASH and SRAM(16bit & 8bit).
- Interface support for byte addressable 16bit devices(UB_N & LB_N signals).
- 2Mbytes of memory per chip select.
- Support for 8 bit/16bit wide NAND flash.
- Support for parallel LCD interfaces, port mapped of memory mapped(8 or 16 bit)
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