Rselo - Denon D-107 Service Manual

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LA6559 (IC201)
REV 1
Signal System VCC
S-VCC 2
Input
Power Supply
(Forward/Reverse/
(LOADING)
VCC2 3
Break/OFF)
VLO- 4
VLO+ 5
VO4+ 6
VO4- 7
VO3+ 8
VO3- 9
Power
System
GND
FR FR
VO2+ 10
VO2- 11
VO1+ 12
VO1- 13
VCC1 14
Power Supply
(CH1 to CH4)
VIN1 15
VIN1- 16
33k
11k
VIN1+ 17
VIN2 18
TE
L 13942296513
LC32V4265T-25
(IC208)
V 1
CC
I/O1 2
I/O2 3
I/O3 4
I/O4 5
V 6
CC
I/O5 7
I/O6 8
I/O7 9
TOP VIEW
I/O8 10
N.C. 11
N.C. 12
WE 13
RAS 14
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N.C. 15
A0 16
A1 17
A2 18
A3 19 .
V 20
CC
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Thermal
Shutdown
36 FWD
Signal System GND
35 S-GND
CH2 to CH4
MUTE2 34 MUTE2
Output
CH1 Output
33 MUTE1
MUTE1
ON/OFF
32 VIN4
33k
31 VIN4-
11k
30 VIN4+
29 VREF-IN
28 VCONT(LOADING)
Power System GND
FR FR
PNP Tr
Collector
27 REG-OUT
3.3VREG
PNP Tr
(External PNP)
Base
26 REG-IN
33k
25 VIN3+
11k
24 VIN3-
23 VIN3
3.3VREG GND
22 GND-VREG
3.3VREG
Power Supply
21 VCC-VREG
33k
20 VIN2+
11k
19 VIN2-
40 V
SS
39 I/O16
RAS Clock Generator No.1
38 I/O15
UCAS
37 I/O14
LCAS
36 I/O13
35 V
SS
34 I/O12
33 I/O11
32 I/O10
31 I/O9
30 N.C.
29 LCAS
A0
28 UCAS
27 OE
26 A8
25 A7
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24 A6
23 A5
22 i A4
21 V
SS
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2 9
8
Pin
Name
No.
5CH output change terminal, logic input of
1 REV
loading block
signal system power supply
2 S-Vcc
(BTL-AMP:CH1~4)
3 Vcc2 Power supply for loading block
4 VL0− Loading output (−)
5 VL0+ Loading output (+)
6 VO4+ Output terminal (+) for channel 4
7 VO4− Output terminal (−) for channel 4
8 VO3+ Output terminal (+) for channel 3
9 VO3− Output terminal (−) for channel 3
10 VO2+ Output terminal (+) for channel 2
11 VO2− Output terminal (−) for channel 2
12 VO1+ Output terminal (+) for channel 1
13 VO1− Output terminal (−) for channel 1
14 Vcc1 CH1 CH4(BTL-AMP) output stage power supply
15 VIN1 Input terminal for channel 1
16 VIN1− OP-AMP input AMP-A input terminal (−)
17 VIN1+ OP-AMP input AMP-A input terminal (+)
18 VIN2 Input terminal for channel 2, input AMP output
19 VIN2− Input terminal (−) for channel 2
20 VIN2+ Input terminal (+) for channel 2
21 Vcc-VREG 3.3VREG power supply
22 GND-VREG 3.3VREG GND
23 VIN3 Input terminal for channel 3, input AMP output
24 VIN3− Input terminal (−) for channel 3
25 VIN3+ Input terminal (+) for channel 3
Q Q
26 REG-IN 3 6 7 1 3 PNP transistor base connected 1 5
3.3V power output to which the PNP transistor
27 REG-OUT
collector connected
28 VCONT Loading output voltage set terminal
29 VREF-IN Reference voltage applied terminal
30 VIN4+ Input terminal (+) for channel 4
31 VIN4- Input terminal (−) for channel 4
32 VIN4 Input terminal for channel 4, input AMP output
33 MUTE1 Output ON/OFF for channel 1 (BTL AMP)
34 MUTE2 Output ON/OFF for channel 2 to 4 (BTL AMP)
35 S-GND Signal system GND
Output change terminal (FWD) for loading
36 FWD
output (VLO+−), logic input of loading block
Clock Generator No.2
Mode Control
Refresh Counter
262144 Memory Cell
512
x16 Bit
Row Address
Buffer
512x16
Sense Amp
I/O Gate
512
co
Column Address Column Decoder
Buffer Pre-Decoder
.
9 4 2 8
Function
0 5 8 2 9 9 4 2 8
Clock Generator No.3
Lower Byte Upper Byte
Data Input Buffer
I/O1 I/O8 I/O9 I/O16
Data Output Buffer
I/O1 I/O8 I/O9 I/O16
m
PWB Bias Generator
D-107
9 9
9 9
Vcc
Vss
WE
I/O1
I/O16
OE
27