Toshiba TDP-P75 Service Manual page 18

TDP-P75 Service Manual
designated IR0 and IR1 have the following characteristics:
.... Voltage Level: LVTTL (3.3 VDC)
.... Maximum Frequency: 1 MHz
.... Typical Frequency: 2 KHz
.... Noise immunity: See the Software User's Guide.
4.7.5. Power Monitor and Reset
There are 3 inputs to the DDP2000 ASIC used for initialization, reset, and power
monitoring.
POSENSE ("power on" sense) is a signal which must be generated by an external power
monitor IC, as shown in the reference design. POSENSE should be asserted low only
during initial application of power to the projector system. The DDP2000 is immediately
and ASYNCHRONOUSLY reset, without regard to the DMD status. The DMD mirror park
sequence is NOT performed in this case. The power-up initialization sequence requires
at least 165ms after POSENSE goes high. PWSENSE should remain low until the core
voltage is greater than 1.3V
PWRGOOD is a high true signal which indicates that all supplies are within operational
limits. Ideally this signal is generated near the front-end of the system power supply, so
that there will be some advance indication of power loss. When PWRGOOD goes low,
the DMD mirrors are "parked" prior to reset of the ASIC and external devices. The time
required to "park" the DMD mirrors is typically 1 msec.
SYSRSTZ is a general purpose reset and causes the DMD mirrors to be "parked" prior to
reset of the ASIC and external devices. A typical use of the SYSRSTZ signal is for
processor initialization following lamp ignition.
For a "normal" power down event, the system design must ensure that PWRGOOD (or
SYSRSTZ) goes low prior to POSENSE low, so that enough time exists for the mirror park
sequence to complete successfully.
4.7.6. UART
There are two separate UART ports on the DDP2000 ASIC. Each port contains the
following signals:
.... UARTx_TXD: Transmit data
.... UARTx_RXD: Receive Data
.... UARTx_CTS: Clear to Send
.... UARTx_RTS: Ready to Send
Please see section 6 for details on using a UART to support a lamp ballast
communication path.
The recommended operating conditions for the TXD and RTS signals are given in section
2 and include the following:
Sink current: 16 mA maximum
Source Current: 16 mA maximum
The input buffers for the RXD and CTS signals have the following recommended
operating conditions:
High Level Input Current ( H): -10 uA to +10 uA
II
Low Level Input Current ( L): -10 uA to +10 uA
II
4.7.7. I2C
The DDP2000 supports an I C bus up to 400 KHz. The dedicated pins are as follows:
2
.... SCL0
.... SDA0
For interface definition, please see the I C bus specification.
2
The recommended operating conditions for these signals are given in section 2 and
include the following:
Sink current: 16 mA maximum
Source Current: 16 mA maximum
4.7.8. JTAG IEEE 1149.1 (JTAG) Test Port
The DDP2000 ASIC provides a standard IEEE 1149.1 (JTAG) test port. TI highly
recommends utilizing the JTAG port for in-circuit-test (ICT) board test.
4.7.9. Dedicated Test Points
Eight test points, TSTPT(7:0) are available. Those signals are routed from the DDP2000
to the Test Point header located on the reference design board. Each of the eight signals
is an output only. See the software User's Guide for information regarding programming
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08/19/05