Toshiba TDP-P75 Service Manual page 16

TDP-P75 Service Manual
4.5. Clock Circuitry
4.5.1. Clocks
4.5.1.1. Reference Clock
The DDP2000 is designed to support both DRCG based Rambus™ memory operation
and DRCG-Lite Rambus™ memory operation.
4.5.1.2. DRCG
In regular DRCG operation, an external DRCG clock IC (CDCR83) aligns the Rambus™
memory channel clocks with an otherwise unrelated clock system inside the ASIC. This is
done by phase adjusting the Rambus™ memory channel clocks into alignment with an
external reference. In this case, an external 50MHz oscillator IC is required.
The DDP2000 ASIC uses a divide by 5 circuit to arrive at a 10 MHz reference clock for all
other timing.
4.5.1.3. DRCG-Lite
The DRCG-Lite Rambus™ memory clocking topology uses a special, lower cost "DRCG-Lite"
clock driver (CDCR61A) that derives the Rambus™ memory channel clocks from a
low cost 18.75MHz crystal, and provides no ability to phase align the Rambus™ memory
clock. Rather, it is assumed that the clocking system within the ASIC will align itself to the
Rambus™ memory channel. This is accomplished by using a PLL to phase lock the
internal 100MHz memory clock with the Rambus™ memory clock signal.
A second output of the DRCG-Lite is the LCLK which is configured to output a clock at ½
the input rate, or 9.375 MHz. The DDP2000, in the DRGC-Lite mode, uses the 9.375
MHZ clock for reset timing.
4.6. Lamp and Ballast
4.6.1. Lamp and Ballast Overview
The DDP2000 ASIC is compatible with a variety of lamp/ballast combinations. The
communication between the ballast and the DDP2000 ASIC requires two signals, and may
also include a serial data link if the ballast is so equipped.
4.6.2. Discrete signals
The DDP2000 electronics can control a variety of DC and AC type lamp ballasts. The
DDP2000 electronics provides a lamp enable (LAMPEN) signal for lamp control and a
lamp lit (LAMPLITZ) signal for status from the lamp ballast.
4.6.3. Lamp Enable – LAMPEN
The DDP2000 electronics provides a lamp enable (LAMPEN) signal to control the projector
lamp and ballast. The LAMPEN is used for on/off control as well as synchronization of AC
lamps.
The state of LAMPEN after a reset is low. This is normally the off state of the lamp ballast.
Once PWRGOOD and RESETZ are high and the color wheel is spinning at speed, the
DPP2000 electronics drives the LAMPEN high. For AC and DC ballasts it is assumed that
the lamp ballast will ignite the lamp when LAMPEN is driven from low to high. For AC
lamps the ballast must drive the lamp with internal synchronization if LAMPEN is held high.
The LAMPEN signal can also be used to synchronize an AC lamp, once the lamp is lit and
stable. The DDP2000 ASIC can output lamp synchronization timing on the LAMPEN. The
DDP2000 ASIC supports two types of lamp synchronization signaling:
.... Level
.... Rising edge
In the level synchronization mode, the level of the LAMPEN controls the direction of the
current to the lamp.
The second type of synchronization is referred to as rising edge. In this mode, the rising
edge of the LAMPEN causes the current to the lamp to alternate.
4.6.4. Lamp Lit – LAMPLITZ
The LAMPLITZ signal shall be asserted to the DDP2000 electronics after successful
ignition of the projector lamp. The transition of LAMPLITZ from high to low may be used
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