Integra NAC-2.3 Service Manual page 31

Audio network receiver
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BLOCK DIAGRAM AND PIN DESCRIPTION OF IC - 6
Q611:AK4353
DAC WITH DIT
No.
Pin Name
1
MCKO
2
TX
3
DVDD
4
DVSS
5
MCKI
6
BICK
7
SDTI
8
LRCK
9
PDN
10
CSN
11
SCL
CCLK
12
SDA
CDTI
13
TST
14
TTL
15
I2C
16
CAD0
17
CAD1
18
AOUTR
19
AOUTL
20
VCOM
21
AVSS
22
AVDD
23
NC
24
DZF
PIN/FUNCTION
I/O
O
Master Clock Output Pin
Same frequency as MCKI is output
O
Transmit Channel Output Pin
-
Digital Power Supply Pin, +2.7∼+5.5V
-
Digital Ground Pin, 0V
I
Master Clock Input Pin
I
Serial Data Clock Pin
I
Serial Data Input Pin
I
Serial Input Channel Clock Pin
I
Power-Down Pin
When "L", the circuit is in power-down mode.
The AK4353 should always be reset upon power-up.
I
Chip Select Pin at 3-wire Serial control mode
This pin should be connected to DVDD at I
2
I
Control Clock Pin at I
C bus control mode
I
Control Clock Pin at 3-wire serial control mode
I/O
Control Data Input/Output Pin at I
I
Control Data Input Pin at 3-wire serial control mode
I
Test pin
This pin should be connected to DVDD.
I
Digital Input Level Select Pin
"L": CMOS, "H": TTL
I
Control Mode Select Pin
"L": 3-wire Serial, "H": I
I
Chip Address Select 0 Pin
I
Chip Address Select 1 Pin
O
Rch Analog Output Pin
O
Lch Analog Output Pin
O
Common Voltage Output Pin, AVDD/2
Used for analog common voltage.
Large external capacitor is used to reduce power supply noise.
-
Analog Ground Pin
-
Analog Power Supply Pin
-
No Connect
Nothing should be connected externally to this pin.
O
Zero Input Detect Pin
When SDTI follows a total 8192 LRCK cycles with "0" input data
or RSTN = "0", this pin goes to "H".
Description
2
C Bus control mode.
2
C Bus control mode
2
C Bus
NAC-2.3

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